module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    //首先创建一个8位的移位寄存器
    reg [7:0] Q;
    reg [6:0] Q_next;
    always @(posedge clk)
        begin
            Q_next = Q[7:1];
            if (enable)
                Q <= {S,Q_next};
        end
    
    always @(*)
        begin
            case({A,B,C})
                3'b000: Z = Q[7];
                3'b001: Z = Q[6];
                3'b010: Z = Q[5];
                3'b011: Z = Q[4];
                3'b100: Z = Q[3];
                3'b101: Z = Q[2];
                3'b110: Z = Q[1];
                3'b111: Z = Q[0];
            endcase
        end

endmodule