End of Moore's Law up with emerging opportunities in HW/SW in DSA/DSL

Hardware is getting harder

• modern compute acceleration platforms are multi-level and explicit
• heterogeneous compute incorporating domain-specific accelerators
• many accelerator IPs are configurable

Next-Gen compilers and PL are needed

• hardware abstraction spanning diverse accelerators;
• support for heterogeneous compute platforms;
• domain-specific languages and programming models;
• quality, reliability, and scalability of infrastructure

fragmentation of DSL is not good for innovation
extract common places which they may have solutions before, we don't want to reinvent them. Not co-design with Arch..

Modular and subset-able ISA design( RISC-V)
eg: small RV core as the control unit, combined with a large hard-coded domain-specific core

Scalability allows full spectrum of design points
RISC-V Compiler + Kernel Drivers

compilers for hardware, accelerate the HW design process