module top(
       input sys_clk_50m,
	   input sys_rst_n,
	   
	   output [2:0] vga_r,
	   output [2:0] vga_g,
	   output [1:0] vga_b,
	   output vga_hsy,
	   output vga_vsy
    );
	

	
	vga_countroller uut_vga_countroller (
    .clk(sys_clk_50m), 
    .rst(sys_rst_n), 
    .vga_r(vga_r), 
    .vga_g(vga_g), 
    .vga_b(vga_b), 
    .vga_hsy(vga_hsy), 
    .vga_vsy(vga_vsy)
    );


endmodule

module vga_countroller(
       input clk,
	   input rst,
	   
	   output [2:0] vga_r,
	   output [2:0] vga_g,
	   output [1:0] vga_b,
	   output reg vga_hsy,
	   output reg vga_vsy
    );
	
	//VGA_Timeing 800*600 & 50MHZ & 72MHZ
	parameter VGA_HTT = 12'd1040-12'd1;//Hor Total Time 行帧长
	parameter VGA_HST = 12'd120;       //Hor Sync Time 同步脉冲
	parameter VGA_HBP = 12'd64;        //Hor Back Porch 后沿脉冲
	parameter VGA_HVT = 12'd800;       //Hor Valid Time 显示脉冲
	parameter VGA_HFP = 12'd56;        //Hor Front Porch 前沿脉冲
	
	parameter VGA_VTT = 12'd666-12'd1; //Hor Total Time 列帧长
	parameter VGA_VST = 12'd6;         //Hor Sync Time 同步脉冲
	parameter VGA_VBP = 12'd23;        //Hor Back Porch 后沿脉冲
	parameter VGA_VVT = 12'd600;       //Hor Valid Time 显示脉冲
	parameter VGA_VFP = 12'd37;        //Hor Front Porch 前沿脉冲
	
	parameter VGA_CORBER = 12'd100;    //8等分做colorbar显示
	
	
	//X和Y坐标计数器
	reg [11:0] xcnt;
	reg [11:0] ycnt;
	always@(posedge clk or negedge rst)
	 begin
	  if(!rst)
	   xcnt <= 12'd0;
	  else if(xcnt >= VGA_HTT)
	   xcnt <= 12'd0;
	  else
	   xcnt <= xcnt + 1'b1;
	 end
	 
	always@(posedge clk or negedge rst)
	 begin
	  if(!rst)
	   ycnt <= 12'd0;
	  else if(xcnt == VGA_HTT)
	   begin
	    if(ycnt >= VGA_VTT)
	     ycnt <= 12'd0;
  		else
         ycnt <= ycnt + 1'b1;
	   end
	  else
	   ycnt <= ycnt;
	 end
	 
	//行信号生成
	always@(posedge clk or negedge rst)
	 begin
	  if(!rst)
	   vga_hsy <= 1'b0;
	  else if(xcnt<VGA_HST)
	   vga_hsy <= 1'b1;
	  else
	   vga_hsy <= 1'b0;
	 end
	 
	 
	//场信号生成
	always@(posedge clk or negedge rst)
	 begin
	  if(!rst)
	   vga_vsy <= 1'b0;
	  else if(ycnt<VGA_VST)
	   vga_vsy <= 1'b1;
	  else
	   vga_vsy <= 1'b0;
	 end
	 
	//显示有效区域标志信号生成
	reg vga_valid;//显示区域内，该信号为高电平
	always@(posedge clk or negedge rst)
	 begin 
	  if(!rst)
	   vga_valid <= 1'b0;
	  else if(xcnt>=(VGA_HST+VGA_HBP) && xcnt<(VGA_HST+VGA_HBP+VGA_HVT) && ycnt>=(VGA_VST+VGA_VBP) && ycnt<(VGA_VST+VGA_VBP+VGA_VVT))
	   vga_valid <= 1'b1;
	  else
	   vga_valid <= 1'b0;
	 end
	 
	//产生颜色逻辑
	reg vga_rdb;
	reg vga_gdb;
	reg vga_bdb;
	always@(posedge clk or negedge rst)
	 begin
	  if(!rst)
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b0;
		vga_bdb = 2'b0;
	   end
	  // else if(xcnt==(VGA_HST+VGA_HBP))//绿色边框
	   // begin
	    // vga_rdb = 3'b0;
		// vga_gdb = 3'b0;
		// vga_bdb = 2'b11;
	   // end
	  // else if(xcnt<=(VGA_HST+VGA_HBP+VGA_HVT-4'd1))//绿色边框
	   // begin
	    // vga_rdb = 3'b0;
		// vga_gdb = 3'b0;
		// vga_bdb = 2'b11;
	   // end
	  // else if(ycnt<=(VGA_VST+VGA_VBP))//绿色边框
	   // begin
	    // vga_rdb = 3'b0;
		// vga_gdb = 3'b0;
		// vga_bdb = 2'b11;
	   // end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER)//1
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b0;
		vga_bdb = 2'b0;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd2)//2
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b0;
		vga_bdb = 2'b11;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd3)//3
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b101;
		vga_bdb = 2'b0;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd4)//4
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b101;
		vga_bdb = 2'b11;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd5)//5
	   begin
	    vga_rdb = 3'b101;
		vga_gdb = 3'b0;
		vga_bdb = 2'b0;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd6)//6
	   begin
	    vga_rdb = 3'b101;
		vga_gdb = 3'b0;
		vga_bdb = 2'b11;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd7)//7
	   begin
	    vga_rdb = 3'b101;
		vga_gdb = 3'b101;
		vga_bdb = 2'b0;
	   end
	  else if(xcnt <= VGA_HST + VGA_HBP + VGA_CORBER*4'd8)//8
	   begin
	    vga_rdb = 3'b101;
		vga_gdb = 3'b101;
		vga_bdb = 2'b11;
	   end
	  else
	   begin
	    vga_rdb = 3'b0;
		vga_gdb = 3'b0;
		vga_bdb = 2'b0;
	   end
	 end
	 
	assign vga_r = vga_valid ? vga_rdb : 3'b0;
	assign vga_g = vga_valid ? vga_gdb : 3'b0;
	assign vga_b = vga_valid ? vga_bdb : 2'b0;
	
	   
	


endmodule