IEEE Standard for Verilog Hardware Description Language

英语说明阅读，首先看导读、目录、摘要等内容。

摘要：

1 Abstract: The Verilog hardware description language (HDL) is defined in this standard. Verilog
2 HDL is a formal notation intended for use in all phases of the creation of electronic systems. Be-
3 cause it is both machine-readable and human-readable, it supports the development, verification,
4 synthesis, and testing of hardware designs; the communication of hardware design data; and the
5 maintenance, modification, and procurement of hardware. The primary audiences for this standard
6 are the implementors of tools supporting the language and advanced users of the language.
7 Keywords: computer, computer languages, digital systems, electronic systems, hardware, hard-
8 ware description languages, hardware design, HDL, PLI, programming language interface, Verilog,
9 Verilog HDL, Verilog PLI

这个格式是不是类似一篇论文，可能就是某个论文或者论文期刊发布的。首先介绍了这个文档的作用是定义verilog，然后说明了verilog的作用是完成电子系统的每个阶段设计。其优点在于可以机读和认读，减少了机器到人之间的距离。支持的有开发、验证、 维护、修改和采购硬件。主要面对的对象是支持该语言的工具使用者及高级用户。

关键词一大堆，可能用于索引。

Introduction
The Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-
1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard
textual format for a variety of design tools, including verification simulation, timing analysis, test analysis,
and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice
by an overwhelming number of integrated circuit (IC) designers.
Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,
and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is
essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in
which expressions of both variables and nets can continuously drive values onto nets, provide the basic
structural construct. Procedural assignments, in which the results of calculations involving variable and net
values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-
ules, each of which has an input/output (I/O) interface, and a description of its function, which can be struc-
tural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.
The Verilog language is extensible via the programming language interface (PLI) and the Verilog proce-
dural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access
information contained in a Verilog HDL description of the design and facilitates dynamic interaction with
simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation
and computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, and
annotators.
The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer-
sity in England under a contract to produce a test generation system for the British Ministry of Defense.
HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification
simulation, timing analysis, fault simulation, and test generation.
In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent
Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of
Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE
working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as
IEEE Std 1364-1995.
After the standardization process was complete, the IEEE P1364 Working Group started looking for feed-
back from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This
led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001.
With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify
outstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-
ing on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led to
incompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was estab-
lished as a subcomittee of the SystemVerilog P1800 Working Group to help ensure consistent resolution of
such issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.

这部分是简介部分。在原文中还有注释，这个不是文档内容，可能是后加的。

大致意思：

1995年，verilog成为标准。由于简单、直观、有效，可以在多个设计层次使用，成为IC工作者的重要语言。

verilog结构丰富，有逻辑门、用户定义体、开关、线逻辑。提供门级延时和时序检查。两种形式的数据：net和variable，也就是wire和reg声明的对象类型。在行为综合时的net和variable报错也是这两种数据类型。然后就是module的结构。

verilog可以通过PLI和VPI拓展，可以增加其他函数。modelsim在激励源支持的函数就是这里而来。

verilog的前身是HILO-2，是Brunel大学创建的。

后面则是介绍verilog的发展历史，就不做说明，感兴趣可以看一下。