2 参考文档《pg168-gtwizard》《ug476_7Series_Transceivers》
3 GTX的IP设置本例程使用环境编译环境:vivado 2017.4选用FPGA:XC7K325C-2FFG900
GTX IP界面的设置情况本例程使用GTX主要是实现SMA口,而不是PCIE,SATA等特殊协议。采用的编码形式为8B/10B,对齐字符为K码。本例程的IP设置情况如下所示:
GTX IP设置第1页第1页设置主要是GT的类型,这个一般根据器件会确定默认选择,高端器件可能有两种根据自己需要的速率设置即可。GTX IP设置第2页通过上文的介绍,我们知道SMA口在GTX bank117里面 所以打开GTX_X0Y8通道 时钟选择REFCLK1 Q2GTX IP设置第3页具体参数如下
Option | I/O | Description |
TXPCSRESET | Input | Active-High reset signal for the transmitter physical coding sublayer (PCS) logic. |
TXBUFSTATUS | Output | 2-bit signal monitors the status of the TX elastic buffer. This option is not available when the TX buffer is bypassed. |
TXRATE | Input | Transmit rate change port. |
RXPCSRESET | Input | Active-High reset signal for the receiver PCS logic. |
RXBUFSTATUS | Output | Indicates condition of the RX elastic buffer. Option is not available when the RX buffer is bypassed. |
RXBUFRESET | Input | Active-High reset signal for the RX elastic buffer logic. This option is not available when the RX buffer is bypassed. |
RXRATE | Input | Receive rate change port. |
QPLLPD | Input | Visible only when GTX or GTH transceiver is selected. Powerdown port for QPLL. |
CPLLPD | Input | Visible only when GTX or GTH transceiver is selected. Powerdown port for channel PLL (CPLL). |