等待硬件事件

虽然通常driver会负责正常的硬件同步，但sequence运行过程中可能需要与硬件事件同步，例如边界信号的转换或复位事件的结束。 不应该去修改driver然后为sequence_item添加一个新的字段，而是建议在包含指向virtual interface的指针的配置对象中实现 wait_for_hardware_event 方法。

举个例子，可以利用一个配置类，内含虚接口，传递给sequence，然后在配置类中实现相关方法。

///// Transaction Class
class transaction extends uvm_sequence_item;
	`uvm_object_utils(transaction)
 
	rand logic [31:0] addr;
	rand logic [31:0] write_data;
 	rand bit read;
	rand int delay;
 
	bit error;
	logic [31:0] read_data;
 
	function new (string name);
		super.new(name);
	endfunction: new
 
	constraint at_least_1 { delay inside {[1:20]};}
 
	constraint 32bit_align {addr[1:0] == 0;}
 
endclass: transaction

///// Bus Configuration Object
class bus_config extends uvm_object;
	`uvm_object_utils(bus_config)
 
	virtual bus_interface bus_if;
 
	function new (string name);
		super.new(name);
	endfunction: new
 
 /// wait_for_clock
	task wait_for_clock( int m = 1 );
		repeat ( m ) begin
			@(posedge bus_if.clk);
		end
	endtask: wait_for_clock
 
 /// wait_for_reset
	task wait_for_reset;
		@(posedge bus_if.reset);
	endtask: wait_for_reset
 
endclass: bus_config

///// Bus Sequence
class bus_seq extends uvm_sequence #(transaction);
	`uvm_object_utils(bus_seq)
 
	transaction txn;
	bus_config bus_cfg;
 
	rand int limit = 25;
 
	function new (string name);
		super.new(name);
	endfunction: new
 
	task body;
		int i = 5;
		txn = transaction::type_id::create("txn", this);
 /// Get the Configuration object
		if(!uvm_config_db #(bus_config)::get(null, get_full_name(), "config", bus_cfg)) begin
			`uvm_error(" SEQ BODY ", "bus_config is not found")
		end
    repeat (limit) begin
			start_item(txn);
			if(!txn.randomize() with {addr inside {[32‘h0010_0000:32‘h0010_001C]};}) begin
				`uvm_error(" SEQ BODY ", " Transaction randomization failed")
			end
			finish_item(txn);
 /// wait for interface clock
			bus_cfg.wait_for_clock(i);
			i++;
 /// The txn handle points to the object that the driver has updated with response data
			`uvm_info(" SEQ BODY ", " txn.read_data ", UVM_LOW)
 		end
	endtask: body
endclass: bus_seq

引用Wait for Interface Signals in UVM | Universal Verification Methodology (learnuvmverification.com)

UVM实用技巧【二】