1 消息提示：

Critical Warning (10237): Verilog HDL warning at edge_check.v(12): can‘t infer register for assignment in edge-triggered always construct because the clock isn‘t obvious. Generated combinational logic instead

2 现象及产生原因：

3.解决方案：

（1）删去“ or negedge rst_n”;

（2）补充完整，给出复位操作，如下所示

Critical Warning (10237): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead