前五个Verilog代码实现

（不一定对，欢迎指正）

1. SM

module SM (
    input clk,sm_en,
    output reg sm
);
always @(negedge clk or negedge sm_en) begin
    if(sm==1'bz)begin sm=1'b0;end
    if(~sm_en)begin
        sm<=1'bz;
    end
    else begin
        sm<=~sm;
    end
end    
endmodule

2、指令寄存器IR

module IR (
    input clk,ir_ld,
    input [7:0] d,
    output reg [7:0] ir
);
always @(negedge clk or negedge ir_ld) begin
    if(~ir_ld)begin
        ir<=1'bz;
    end
    else begin
        ir<=d;
    end
end    
endmodule

3、状态寄存器PSW

module PSW (
    input clk,cf_en,zf_en,
    input cf,zf,
    output reg c,z
);
always @(negedge clk or negedge cf_en) begin
    if(~cf_en)begin
        c<=1'bz;
    end
    else begin
        c<=cf;
    end
end
always @(negedge clk or negedge zf_en) begin
    if(~zf_en)begin
        z<=1'bz;
    end
    else begin
        z<=zf;
    end
end    
endmodule

4、指令计数器PC

module PC (
    input clk,pc_inc,pc_ld,
    input [7:0] a,
    output reg[7:0] add
);
always @(negedge clk) begin
    if(pc_inc==1'b1&&pc_ld==1'b0)begin
        add<=add+1'b1;
    end
    else if(pc_inc==1'b0&&pc_ld==1'b1) begin
        add<=a;
    end
    else begin add<=add;end
end    
endmodule

5、通用寄存器组

module group (
    input clk,we,
    input [1:0] raa,rwba,
    input [7:0] i,
    output reg[7:0] s,d
);
reg[7:0] A=1'bx,B=1'bx,C=1'bx; 
parameter a=2'b00,b=2'b01,c=2'b10;   
always @(raa or rwba or A or B or C) begin
    case (raa)
    a:begin s=A;end
    b:begin s=B;end
    c:begin s=C;end
    default:begin s=1'bz;end
    endcase
    case (rwba)
    a:begin d=A;end
    b:begin d=B;end
    c:begin d=C;end
    default:begin d=1'bz;end
    endcase
end
always @(negedge clk) begin
    if(we==1'b0)begin
        case (rwba)
        a:begin A<=i;end
        b:begin B<=i;end
        c:begin C<=i;end
        endcase
    end
    else begin A<=A;end//it is useless
end
endmodule