X-007 FriendlyARM tiny4412 u-boot移植之内存初始化

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开发环境:win7 64位 + VMware12 + Ubuntu14.04 64位

工具链:linaro提供的gcc-linaro-6.1.1-2016.08-x86_64_arm-linux-gnueabi

要移植的u-boot版本:u-boot-2016-11

Tiny4412开发板硬件版本为

    底板:  Tiny4412/Super4412SDK 1506

       核心板:Tiny4412 - 1412

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 

在上一节中我们把tiny4412开发板上的COM0串口用起来,可以通过COM0串口输出一些调试信息。接下来要做的是初始化tiny4412开发板上的DDR3内存。

1、Tiny4412开发板上的DDR3内存

   原理图:Tiny4412-1412-Schematic.pdf

X-007 FriendlyARM tiny4412 u-boot移植之内存初始化

从原理图上可以看出,使用2片K4B4G1646B-HCK内存芯片并联组成了数据位为32bit 1G大小的内存。内存芯片接在exynos4412芯片的DMC0上,使用了一个chip(chip0),内存地址空间为0x40000000-0x80000000。

2、Exynos4412芯片DMC初始化步骤

具体信息在 《Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary.pdf》第18章Dynamic Memory Controller

X-007 FriendlyARM tiny4412 u-boot移植之内存初始化

X-007 FriendlyARM tiny4412 u-boot移植之内存初始化

3、Tiny4412 DDR3初始化代码

diff --git a/arch/arm/mach-exynos/dmc_init_exynos4412.c b/arch/arm/mach-exynos/dmc_init_exynos4412.c

new file mode 100644

index 0000000..27f72cd

--- /dev/null

+++ b/arch/arm/mach-exynos/dmc_init_exynos4412.c

@@ -0,0 +1,254 @@

+/*

+ * Memory setup for board based on EXYNOS4412

+ *

+ *                 2016

+ * Modified by AP0904225 <ap0904225@qq.com>

+ *

+ * Copyright (C) 2013 Samsung Electronics

+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>

+ *

+ * See file CREDITS for list of people who contributed to this

+ * project.

+ *

+ * This program is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU General Public License as

+ * published by the Free Software Foundation; either version 2 of

+ * the License, or (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program; if not, write to the Free Software

+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

+ * MA 02111-1307 USA

+ */

+

+#include <config.h>

+#include <asm/arch/dmc.h>

+#include "common_setup.h"

+#include "exynos4412_setup.h"

+

+#ifdef TINY4412

+struct mem_timings mem = {

+   .direct_cmd_msr = {

+       DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4

+   },

+   .timingref   = 0x000000BB,

+   .timingrow   = 0x6946654f,

+   .timingdata  = 0x46460506,

+   .timingpower = 0x5200183c,

+   .zqcontrol   = 0xE3854C03,

+   .control0    = 0x71101008,

+   .control1    = 0xe0000086,

+   .control2    = 0x00000000,

+   .concontrol  = 0x0FFF301A,

+   .prechconfig = 0xff000000,

+   .memcontrol  = 0x00302640,      /* Tiny4412-1412 core board only use chip0 */

+   .memconfig0  = 0x40C01333,      /* ROW is 15bit */

+   .memconfig1  = 0x80C01333,      /* DMC0 address up to 0x7FFFFFFF */

+   .dll_resync  = FORCE_DLL_RESYNC,

+   .dll_on      = DLL_CONTROL_ON,

+

+};

+#else

+struct mem_timings mem = {

+   .direct_cmd_msr = {

+       DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4

+   },

+   .timingref = TIMINGREF_VAL,

+   .timingrow = TIMINGROW_VAL,

+   .timingdata = TIMINGDATA_VAL,

+   .timingpower = TIMINGPOWER_VAL,

+   .zqcontrol = ZQ_CONTROL_VAL,

+   .control0 = CONTROL0_VAL,

+   .control1 = CONTROL1_VAL,

+   .control2 = CONTROL2_VAL,

+   .concontrol = CONCONTROL_VAL,

+   .prechconfig = PRECHCONFIG,

+   .memcontrol = MEMCONTROL_VAL,

+   .memconfig0 = MEMCONFIG0_VAL,

+   .memconfig1 = MEMCONFIG1_VAL,

+   .dll_resync = FORCE_DLL_RESYNC,

+   .dll_on = DLL_CONTROL_ON,

+};

+#endif

+

+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)

+{

+   if (ctrl_no) {

+       writel((mem.control1 | (1 << mem.dll_resync)),

+              &dmc->phycontrol1);

+       writel((mem.control1 | (0 << mem.dll_resync)),

+              &dmc->phycontrol1);

+   } else {

+       writel((mem.control0 | (0 << mem.dll_on)),

+              &dmc->phycontrol0);

+       writel((mem.control0 | (1 << mem.dll_on)),

+              &dmc->phycontrol0);

+   }

+}

+

+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)

+{

+   int i;

+   unsigned long mask = 0;

+

+   if (chip)

+       mask = DIRECT_CMD_CHIP1_SHIFT;

+

+   for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {

+       writel(mem.direct_cmd_msr[i] | mask,

+              &dmc->directcmd);

+   }

+}

+

+static void dmc_init(struct exynos4_dmc *dmc)

+{

+   /*

+    * DLL Parameter Setting:

+    * Termination: Enable R/W

+    * Phase Delay for DQS Cleaning: 180' Shift

+    */

+   writel(mem.control1, &dmc->phycontrol1);

+

+   /*

+    * ZQ Calibration

+    * Termination: Disable

+    * Auto Calibration Start: Enable

+    */

+   writel(mem.zqcontrol, &dmc->phyzqcontrol);

+   sdelay(0x100000);

+

+   /*

+    * Update DLL Information:

+    * Force DLL Resyncronization

+    */

+   phy_control_reset(1, dmc);

+   phy_control_reset(0, dmc);

+

+   /* Set DLL Parameters */

+   writel(mem.control1, &dmc->phycontrol1);

+

+   /* DLL Start */

+   writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);

+

+   writel(mem.control2, &dmc->phycontrol2);

+

+   /* Set Clock Ratio of Bus clock to Memory Clock */

+   writel(mem.concontrol, &dmc->concontrol);

+

+   /*

+    * Memor Burst length: 8

+    * Number of chips: 2

+    * Memory Bus width: 32 bit

+    * Memory Type: DDR3

+    * Additional Latancy for PLL: 1 Cycle

+    */

+   writel(mem.memcontrol, &dmc->memcontrol);

+

+   writel(mem.memconfig0, &dmc->memconfig0);

+   writel(mem.memconfig1, &dmc->memconfig1);

+

+#ifdef TINY4412

+   writel(0x8000001F, &dmc->ivcontrol);

+#endif

+

+   /* Config Precharge Policy */

+   writel(mem.prechconfig, &dmc->prechconfig);

+   /*

+    * TimingAref, TimingRow, TimingData, TimingPower Setting:

+    * Values as per Memory AC Parameters

+    */

+   writel(mem.timingref, &dmc->timingref);

+   writel(mem.timingrow, &dmc->timingrow);

+   writel(mem.timingdata, &dmc->timingdata);

+   writel(mem.timingpower, &dmc->timingpower);

+

+   /* Chip0: NOP Command: Assert and Hold CKE to high level */

+   writel(DIRECT_CMD_NOP, &dmc->directcmd);

+   sdelay(0x100000);

+

+   /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */

+   dmc_config_mrs(dmc, 0);

+   sdelay(0x100000);

+

+   /* Chip0: ZQINIT */

+   writel(DIRECT_CMD_ZQ, &dmc->directcmd);

+   sdelay(0x100000);

+

+#ifndef TINY4412

+   /* Chip1: NOP Command: Assert and Hold CKE to high level */

+   writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);

+   sdelay(0x100000);

+

+   /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */

+   dmc_config_mrs(dmc, 1);

+   sdelay(0x100000);

+

+   /* Chip1: ZQINIT */

+   writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);

+   sdelay(0x100000);

+#endif

+

+   phy_control_reset(1, dmc);

+   sdelay(0x100000);

+

+   /* turn on DREX0, DREX1 */

+   writel((mem.concontrol | AREF_EN), &dmc->concontrol);

+}

+

+void mem_ctrl_init(int reset)

+{

+   struct exynos4_dmc *dmc;

+

+   /*

+    * Async bridge configuration at CPU_core:

+    * 1: half_sync

+    * 0: full_sync

+    */

+   writel(1, ASYNC_CONFIG);

+

+#ifndef TINY4412

+#ifdef CONFIG_ORIGE

+   /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */

+   writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +

+       APB_SFR_INTERLEAVE_CONF_OFFSET);

+   /* Update MIU Configuration */

+   writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +

+       APB_SFR_ARBRITATION_CONF_OFFSET);

+#else

+   writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +

+       APB_SFR_INTERLEAVE_CONF_OFFSET);

+   writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);

+   writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);

+   writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);

+#ifdef CONFIG_MIU_LINEAR

+   writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);

+   writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);

+   writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);

+   writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);

+   writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +

+       ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);

+#endif

+#endif

+#endif

+

+   /* DREX0 */

+   dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();

+   dmc_init(dmc);

+

+   /* DREX1 */

+   dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl()

+               + DMC_OFFSET);

+   dmc_init(dmc);

+}

diff --git a/arch/arm/mach-exynos/exynos4412_setup.h b/arch/arm/mach-exynos/exynos4412_setup.h

index a05301a..f0a032b 100644

--- a/arch/arm/mach-exynos/exynos4412_setup.h

+++ b/arch/arm/mach-exynos/exynos4412_setup.h

@@ -347,4 +347,199 @@

DIV_MMC4_PRE(DIV_STAT_CHANGING))

+/* Bus Configuration Register Address */

+#define ASYNC_CONFIG       0x10010350

+

+/* DMC */

+#define DIRECT_CMD_NOP 0x07000000

+#define DIRECT_CMD_ZQ  0x0a000000

+#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)

+#define MEM_TIMINGS_MSR_COUNT  4

+#define CTRL_START (1 << 0)

+#define CTRL_DLL_ON    (1 << 1)

+#define AREF_EN        (1 << 5)

+#define DRV_TYPE   (1 << 6)

+

+struct mem_timings {

+   unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];

+   unsigned timingref;

+   unsigned timingrow;

+   unsigned timingdata;

+   unsigned timingpower;

+   unsigned zqcontrol;

+   unsigned control0;

+   unsigned control1;

+   unsigned control2;

+   unsigned concontrol;

+   unsigned prechconfig;

+   unsigned memcontrol;

+   unsigned memconfig0;

+   unsigned memconfig1;

+   unsigned dll_resync;

+   unsigned dll_on;

+};

+

+/* MIU */

+/* MIU Config Register Offsets*/

+#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400

+#define APB_SFR_ARBRITATION_CONF_OFFSET    0xC00

+#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET    0x800

+#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET    0x808

+#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET  0x810

+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET   0x818

+#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820

+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET   0x828

+#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830

+

+

+#ifdef TINY4412

+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */

+#define APB_SFR_INTERLEAVE_CONF_VAL    0x20001507

+#define APB_SFR_ARBRITATION_CONF_VAL   0x00000001

+#endif

+

+#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000

+#define INTERLEAVE_ADDR_MAP_END_ADDR   0xbfffffff

+#define INTERLEAVE_ADDR_MAP_EN     0x00000001

+

+#ifdef CONFIG_MIU_1BIT_INTERLEAVED

+/* Interleave_bit0: 0xC*/

+#define APB_SFR_INTERLEAVE_CONF_VAL    0x0000000c

+#endif

+#ifdef CONFIG_MIU_2BIT_INTERLEAVED

+/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */

+#define APB_SFR_INTERLEAVE_CONF_VAL    0x2000150c

+#endif

+#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR  0x40000000

+#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR        0x7fffffff

+#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR  0x80000000

+#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR        0xbfffffff

+/* Enable SME0 and SME1*/

+#define APB_SFR_SLV_ADDR_MAP_CONF_VAL      0x00000006

+

+#define FORCE_DLL_RESYNC   3

+#define DLL_CONTROL_ON     1

+

+#define DIRECT_CMD1    0x00020000

+#define DIRECT_CMD2    0x00030000

+#define DIRECT_CMD3    0x00010002

+#define DIRECT_CMD4    0x00000328

+

+#define CTRL_ZQ_MODE_NOTERM    (0x1 << 0)

+#define CTRL_ZQ_START      (0x1 << 1)

+#define CTRL_ZQ_DIV        (0 << 4)

+#define CTRL_ZQ_MODE_DDS   (0x7 << 8)

+#define CTRL_ZQ_MODE_TERM  (0x2 << 11)

+#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)

+#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)

+#define CTRL_DCC       (0xE38 << 20)

+#define ZQ_CONTROL_VAL     (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\

+               | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\

+               | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\

+               | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)

+

+#define ASYNC          (0 << 0)

+#define CLK_RATIO      (1 << 1)

+#define DIV_PIPE       (1 << 3)

+#define AWR_ON         (1 << 4)

+#define AREF_DISABLE       (0 << 5)

+#define DRV_TYPE_DISABLE   (0 << 6)

+#define CHIP0_NOT_EMPTY        (0 << 8)

+#define CHIP1_NOT_EMPTY        (0 << 9)

+#define DQ_SWAP_DISABLE        (0 << 10)

+#define QOS_FAST_DISABLE   (0 << 11)

+#define RD_FETCH       (0x3 << 12)

+#define TIMEOUT_LEVEL0     (0xFFF << 16)

+#define CONCONTROL_VAL     (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\

+               | AREF_DISABLE | DRV_TYPE_DISABLE\

+               | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\

+               | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\

+               | RD_FETCH | TIMEOUT_LEVEL0)

+

+#define CLK_STOP_DISABLE   (0 << 1)

+#define DPWRDN_DISABLE     (0 << 2)

+#define DPWRDN_TYPE        (0 << 3)

+#define TP_DISABLE     (0 << 4)

+#define DSREF_DIABLE       (0 << 5)

+#define ADD_LAT_PALL       (1 << 6)

+#define MEM_TYPE_DDR3      (0x6 << 8)

+#define MEM_WIDTH_32       (0x2 << 12)

+#define NUM_CHIP_2     (1 << 16)

+#define BL_8           (0x3 << 20)

+#define MEMCONTROL_VAL     (CLK_STOP_DISABLE | DPWRDN_DISABLE\

+               | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\

+               | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\

+               | NUM_CHIP_2 | BL_8)

+

+

+#define CHIP_BANK_8        (0x3 << 0)

+#define CHIP_ROW_14        (0x2 << 4)

+#define CHIP_COL_10        (0x3 << 8)

+#define CHIP_MAP_INTERLEAVED   (1 << 12)

+#define CHIP_MASK      (0xe0 << 16)

+#ifdef CONFIG_MIU_LINEAR

+#define CHIP0_BASE     (0x40 << 24)

+#define CHIP1_BASE     (0x60 << 24)

+#else

+#define CHIP0_BASE     (0x20 << 24)

+#define CHIP1_BASE     (0x40 << 24)

+#endif

+#define MEMCONFIG0_VAL     (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\

+               | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)

+#define MEMCONFIG1_VAL     (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\

+               | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)

+

+#define TP_CNT         (0xff << 24)

+#define PRECHCONFIG        TP_CNT

+

+#define CTRL_OFF       (0 << 0)

+#define CTRL_DLL_OFF       (0 << 1)

+#define CTRL_HALF      (0 << 2)

+#define CTRL_DFDQS     (1 << 3)

+#define DQS_DELAY      (0 << 4)

+#define CTRL_START_POINT   (0x10 << 8)

+#define CTRL_INC       (0x10 << 16)

+#define CTRL_FORCE     (0x71 << 24)

+#define CONTROL0_VAL       (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\

+               | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\

+               | CTRL_INC | CTRL_FORCE)

+

+#define CTRL_SHIFTC        (0x6 << 0)

+#define CTRL_REF       (8 << 4)

+#define CTRL_SHGATE        (1 << 29)

+#define TERM_READ_EN       (1 << 30)

+#define TERM_WRITE_EN      (1 << 31)

+#define CONTROL1_VAL       (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\

+               | TERM_READ_EN | TERM_WRITE_EN)

+

+#define CONTROL2_VAL       0x00000000

+

+#ifdef TINY4412

+#define TIMINGREF_VAL      0x000000BB

+#define TIMINGROW_VAL      0x4046654f

+#define    TIMINGDATA_VAL      0x46400506

+#define    TIMINGPOWER_VAL     0x52000A3C

+#else

+#define TIMINGREF_VAL      0x000000BC

+#ifdef DRAM_CLK_330

+#define TIMINGROW_VAL      0x3545548d

+#define    TIMINGDATA_VAL      0x45430506

+#define    TIMINGPOWER_VAL     0x4439033c

+#endif

+#ifdef DRAM_CLK_400

+#define TIMINGROW_VAL      0x45430506

+#define    TIMINGDATA_VAL      0x56500506

+#define    TIMINGPOWER_VAL     0x5444033d

+#endif

+#endif

+

+

+

+

+

+

+

+

+

+

#endif /*__EXYNOS4412_SETUP__ */

diff --git a/include/configs/tiny4412.h b/include/configs/tiny4412.h

index 36af8b1..281838d 100644

--- a/include/configs/tiny4412.h

+++ b/include/configs/tiny4412.h

@@ -3,6 +3,9 @@

*     Author AP0904225 <ap0904225@qq.com>

*

* Configuration settings for the FriendlyARM TINY4412 (EXYNOS4412) board.

+ *     FriendlyARM Tiny4412 SDK board hardware version:

+ *           core board   :  Tiny4412-1412

+ *           bottom board :  Tiny4412/Super4412SDK 1506

*

* SPDX-License-Identifier:    GPL-2.0+

*/

@@ -21,11 +24,11 @@

#define CONFIG_SYS_DCACHE_OFF      1

-/* TINY4412 has 4 bank of DRAM */

-#define CONFIG_NR_DRAM_BANKS       4

+/* TINY4412-1412 core board has 8 bank of DRAM */

+#define CONFIG_NR_DRAM_BANKS       8

#define CONFIG_SYS_SDRAM_BASE      0x40000000

#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE

-#define SDRAM_BANK_SIZE            (256 << 20) /* 256 MB */

+#define SDRAM_BANK_SIZE            (128 << 20) /* 128 MB */

/* memtest works on */

#define CONFIG_SYS_MEMTEST_START   CONFIG_SYS_SDRAM_BASE

4、简单测试Tiny4412内存初始化是否正确

完成Exynos4412芯片DMC初始化相关步骤,我们要简单测试下内存是否已经可用。测试方法就是:往指定内存里面写一个值,然后再把该值读出来;如果写入和读取的值相同,就可以认为初始化的内存可以使用了。

测试代码如下:

diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c

index 361727d..0e65242 100644

--- a/arch/arm/mach-exynos/lowlevel_init.c

+++ b/arch/arm/mach-exynos/lowlevel_init.c

@@ -229,7 +229,35 @@ int do_lowlevel_init(void)

#endif

#endif

mem_ctrl_init(actions & DO_MEM_RESET);

+

+       writel(0x44444444, 0x40000000);

+       if(readl(0x40000000) == 0x44444444)

+           printascii("addriss is :0x40000000  ;the value is  0x44444444.... !!!\n\r");

+

+       writel(0x55555555, 0x50000000);

+       if(readl(0x50000000) == 0x55555555)

+           printascii("addriss is :0x50000000  ;the value is  0x55555555.... !!!\n\r");

+

+       writel(0x22222222, 0x50000004);

+       if(readl(0x50000004) == 0x22222222)

+           printascii("addriss is :0x50000004  ;the value is  0x22222222.... !!!\n\r");

+

+       writel(0x66666666, 0x60000000);

+       if(readl(0x60000000) == 0x66666666)

+           printascii("addriss is :0x60000000  ;the value is  0x66666666.... !!!\n\r");

+

+       writel(0x77777777, 0x70000000);

+       if(readl(0x70000000) == 0x77777777)

+           printascii("addriss is :0x70000000  ;the value is  0x77777777.... !!!\n\r");

+

+       writel(0x88888888, 0x7FFFFFFC);

+       if(readl(0x7FFFFFFC) == 0x88888888)

+           printascii("addriss is :0x7FFFFFFC  ;the value is  0x88888888.... !!!\n\r");

+

+

+       #ifndef TINY4412

tzpc_init();

+       #endif

}

return actions & DO_WAKEUP;

编译代码下载到SD卡,从SD卡启动后,串口会打印出如下信息:

UART DEBUG enable .... !!!

addriss is :0x40000000  ;the value is  0x44444444.... !!!

addriss is :0x50000000  ;the value is  0x55555555.... !!!

addriss is :0x50000004  ;the value is  0x22222222.... !!!

addriss is :0x60000000  ;the value is  0x66666666.... !!!

addriss is :0x70000000  ;the value is  0x77777777.... !!!

addriss is :0x7FFFFFFC  ;the value is  0x88888888.... !!!

这样可以初步判断从0x40000000 ~ 0x80000000之间的1G内存是可以使用的。

参考

1、《Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary.pdf》

2、tiny4412sdk-1506原生uboot卡死 http://www.cnblogs.com/kevinhwang/p/5617629.html

3、uboot_tiny4412-20130729

4、DDR3详解(以Micron MT41J128M8 1Gb DDR3 SDRAM为例)之一

http://blog.csdn.net/shanghaiqianlun/article/details/6976804

5、第八章、Tiny4412 U-BOOT移植八 SDRAM工作时序与原理

http://blog.csdn.net/eshing/article/details/37567337

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