module top_module (
input clk,
input reset,
output [9:0] q);
always@(posedge clk)
begin
if(reset)
q <= 10‘b0;
else
begin
if(q == 10‘d999)
q <= 10‘b0;
else
q <= q + 10‘b1;
end
end
endmodule
2.4bit shift register and down counter
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);
reg last_ena1;
reg last_ena2;
always@(posedge clk)begin
if(shift_ena)begin
q <= q << 1;
q[0] <= data;
end
else if(count_ena)begin
q--;
end
end
endmodule
这里提一点，即使是非阻塞的，还是要注意先后顺序。否则还是会出错的。例如这里如果把读数和移位交换就会错误。
3.
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting);
parameter CHECK1 = 3‘b000, CHECK2 = 3‘b001, CHECK3 = 3‘b010, CHECK4 = 3‘b011, DONE = 3‘b100;
reg[2:0] state;
reg[2:0] next_state;
always@(*)begin
case(state)
CHECK1: next_state = (data)? CHECK2 : CHECK1;
CHECK2: next_state = (data)? CHECK3 : CHECK1;
CHECK3: next_state = (data)? CHECK3 : CHECK4;
CHECK4: next_state = (data)? DONE : CHECK1;
DONE : next_state = DONE;
default: next_state = CHECK1;
endcase
end
always@(posedge clk)begin
if(reset)
state <= CHECK1;
else
state <= next_state;
end
always@(posedge clk)begin
if(reset)
start_shifting <= 1‘b0;
else begin
if(next_state == DONE)
start_shifting <= 1‘b1;
end
end
endmodule
4.Enable shift register
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena);
reg[1:0] counter;
always@(posedge clk)begin
if(reset)begin
shift_ena <= 1‘b1;
counter <= 2‘b00;
end
else begin
if(counter == 2‘b11)
shift_ena <= 1‘b0;
else begin
shift_ena <= 1‘b1;
counter <= counter + 2‘b1;
end
end
end
endmodule
5.Review 2015 FSM
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack );
parameter CHECK0 = 3‘b000, CHECK1 = 3‘b001, CHECK2 = 3‘b010, CHECK3 = 3‘b011,
SHIFT = 3‘b100, COUNT = 3‘b101, DONE = 3‘b110;
reg[2:0] state;
reg[2:0] next_state;
reg[2:0] count_shift;
always@(*)begin
case(state)
CHECK0: next_state = (data)? CHECK1 : CHECK0;
CHECK1: next_state = (data)? CHECK2 : CHECK0;
CHECK2: next_state = (data)? CHECK2 : CHECK3;
CHECK3: next_state = (data)? SHIFT : CHECK0;
SHIFT : next_state = (count_shift == 3‘b100)? COUNT : SHIFT;
COUNT : next_state = (done_counting)? DONE : COUNT;
DONE : next_state = (ack)? CHECK0 : DONE;
default: next_state = CHECK0;
endcase
end
always@(posedge clk)begin
if(reset)
state <= CHECK0;
else
state <= next_state;
end
always@(posedge clk)begin
if(reset)begin
shift_ena = 1‘b0;
counting = 1‘b0;
done = 1‘b0;
count_shift = 3‘b0;
end
else begin
case(next_state)
SHIFT: begin shift_ena <= 1‘b1; count_shift++; end
COUNT: begin shift_ena <= 1‘b0; counting <= 1‘b1; end
DONE : begin counting <= 1‘b0; done <= 1‘b1; end
default: begin
shift_ena = 1‘b0;
counting = 1‘b0;
done = 1‘b0;
count_shift = 3‘b000;
end
endcase
end
end
endmodule
6.The complete timer
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack );
parameter CHECK0 = 3‘b000, CHECK1 = 3‘b001, CHECK2 = 3‘b010, CHECK3 = 3‘b011,
SHIFT = 3‘b100, COUNT = 3‘b101, DONE = 3‘b110;
reg[2:0] state;
reg[2:0] next_state;
reg[1:0] shift;
reg[3:0] delay;
reg[9:0] counter;
always@(*)begin
case(state)
CHECK0: next_state = (data)? CHECK1 : CHECK0;
CHECK1: next_state = (data)? CHECK2 : CHECK0;
CHECK2: next_state = (data)? CHECK2 : CHECK3;
CHECK3: next_state = (data)? SHIFT : CHECK0;
SHIFT : next_state = (shift == 2‘b11)? COUNT : SHIFT;
COUNT : next_state = ((count == 4‘b0) && (counter == 999))? DONE : COUNT;
DONE : next_state = (ack)? CHECK0 : DONE;
default: next_state = CHECK0;
endcase
end
always@(posedge clk)begin
if(reset)
state <= CHECK0;
else
state <= next_state;
end
always@(posedge clk)begin
if(reset)begin
end
else begin
if(state == SHIFT)begin
count <= count << 1;
count[0] <= data;
shift <= shift + 2‘b1;
counter <= 10‘b0;
end
else if(state == COUNT)begin
if(counter == 10‘d999)begin
count <= count - 4‘b1;
counter <= 10‘b0;
end
else
counter <= counter + 10‘b1;
end
end
end
assign counting = (state == COUNT);
assign done = (state == DONE);
endmoduleA
7.FSM onehot
module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
reg[9:0] next_state;
// assign B3_next = ...;
// assign S_next = ...;
// etc.
assign next_state[S] = ((~d) && (state[S] | state[S1] | state[S110])) || (state[Wait] && ack);
assign next_state[S1] = d && state[S];
assign next_state[S11] = d && (state[S1] | state[S11]);
assign next_state[S110] = (~d) && (state[S110]);
assign next_state[B0] = d && state[S110];
assign next_state[B1] = state[B0];
assign next_state[B2] = state[B1];
assign next_state[B3] = state[B2];
assign next_state[Count] = (state[B3]) || (state[Count] && (~done_counting)) ;
assign next_state[Wait] = (done_counting) && state[Count] || (state[Wait] && (~ack));
assign B3_next = next_state[B3];
assign S_next = next_state[S];
assign S1_next = next_state[S1];
assign Count_next = next_state[Count];
assign Wait_next = next_state[Wait];
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = (state[B0] || state[B1] || state[B2] || state[B3]);
endmodule
如有错误欢迎讨论和指正。
[练习网址]（https://hdlbits.01xz.net/wiki/Exams/review2015_fsmonehot）