//四级移位寄存器
module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output reg out);
    reg [2:0] Q;
    always @(posedge clk)begin
        if(~resetn)begin
            {Q,out} <= 4'b0;
        end
        else begin
            Q[2] <= in;
            Q[1] <= Q[2];
            Q[0] <= Q[1];
            out <= Q[0];
        end
    end

endmodule