/*******************************************************************************
* I.MX6 U-boot GPIO hacking
* 说明：
* 本文主要记录I.MX6 U-boot是如何设置GPIO口输入输出的，主要是考虑到这个阶段
* 并没有像Linux内核中的gpio_request一系列函数使用。
*
* 2016-3-7 深圳 南山平山村 曾剑锋
******************************************************************************/
cat bootable/bootloader/uboot-imx/board/freescale/mx6q_sabresd/mx6q_sabresd.c
......
#ifdef CONFIG_LCD
void lcd_enable(void)
{
......
mxc_iomux_v3_setup_pad(MX6DL_PAD_SD1_DAT2__GPIO_1_19); ---+
reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR); ---*---------------+
reg |= ( << ); | |
writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR); | |
| |
reg = readl(GPIO1_BASE_ADDR + GPIO_DR); | |
reg &= ~( << ); | |
writel(reg, GPIO1_BASE_ADDR + GPIO_DR); | |
...... | |
} | |
...... | |
| |
#define MX6DL_PAD_SD1_DAT2__GPIO_1_19 <---+ \ |
IOMUX_PAD(0x06D4, 0x02EC, , 0x0000, , NO_PAD_CTRL) | |
| |
/* | |
* configures a single pad in the iomuxer | |
*/ | |
int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) <---+ |
{ |
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; |
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; |
u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; |
u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; |
u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; |
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; |
|
if (mux_ctrl_ofs) |
__raw_writel(mux_mode, base + mux_ctrl_ofs); |
|
if (sel_input_ofs) |
__raw_writel(sel_input, base + sel_input_ofs); |
|
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) |
__raw_writel(pad_ctrl, base + pad_ctrl_ofs); |
|
return ; |
} |
EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); |
|
|
/** |
* 1. 参考文档： |
* i.MX 6Dual/6Quad Multimedia Applications Processor Reference Manual |
* 2. 30.4 Programmable Registers |
* +------------------------------------------------------+ |
* | GPIO memory map | |
* +-----------+-------------------------------+----------+ |
* | Absolute | Register name | Section/ | |
* | address | | page | |
* | (hex) | | | |
* +-----------+-------------------------------+----------+ |
* | 0209_C000 | GPIO data register (GPIO1_DR) | 30.4.1/ | |
* | | | | |
* +-----------+-------------------------------+----------+ |
* 3. GPIO1_BASE_ADDR = 0x1C000 + 0x80000 + 0x02000000 |
* GPIO1_BASE_ADDR = 0x0209C000 |
*/ |
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) <--------+
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) |
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR |
#define AIPS1_ARB_BASE_ADDR 0x02000000 |
|
#define GPIO_GDIR 0x04 <--------+
#define GPIO_DR 0x00