#define CLK_PWRCON_PD_WAIT_CPU_Pos 8 #define CLK_PWRCON_PD_WAIT_CPU_Msk (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) #define CLK_PWRCON_PWR_DOWN_EN_Pos 7 #define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) #define CLK_PWRCON_PD_WU_STS_Pos 6 #define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos) #define CLK_PWRCON_PD_WU_INT_EN_Pos 5 #define CLK_PWRCON_PD_WU_INT_EN_Msk (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) #define CLK_PWRCON_PD_WU_DLY_Pos 4 #define CLK_PWRCON_PD_WU_DLY_Msk (1ul << CLK_PWRCON_PD_WU_DLY_Pos) #define CLK_PWRCON_OSC10K_EN_Pos 3 #define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) #define CLK_PWRCON_IRC10K_EN_Pos 3 #define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_IRC10K_EN_Pos) #define CLK_PWRCON_OSC22M_EN_Pos 2 #define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) #define CLK_PWRCON_IRC22M_EN_Pos 2 #define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_IRC22M_EN_Pos) #define CLK_PWRCON_XTL12M_EN_Pos 0 #define CLK_PWRCON_XTL12M_EN_Msk (1ul << CLK_PWRCON_XTL12M_EN_Pos) #define CLK_AHBCLK_ISP_EN_Pos 2 #define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos) #define CLK_AHBCLK_PDMA_EN_Pos 1 #define CLK_AHBCLK_PDMA_EN_Msk (1ul << CLK_AHBCLK_PDMA_EN_Pos) #define CLK_APBCLK_PS2_EN_Pos 31 #define CLK_APBCLK_PS2_EN_Msk (1ul << CLK_APBCLK_PS2_EN_Pos) #define CLK_APBCLK_I2S_EN_Pos 29 #define CLK_APBCLK_I2S_EN_Msk (1ul << CLK_APBCLK_I2S_EN_Pos) #define CLK_APBCLK_ADC_EN_Pos 28 #define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos) #define CLK_APBCLK_USBD_EN_Pos 27 #define CLK_APBCLK_USBD_EN_Msk (1ul << CLK_APBCLK_USBD_EN_Pos) #define CLK_APBCLK_PWM23_EN_Pos 21 #define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos) #define CLK_APBCLK_PWM01_EN_Pos 20 #define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos) #define CLK_APBCLK_UART1_EN_Pos 17 #define CLK_APBCLK_UART1_EN_Msk (1ul << CLK_APBCLK_UART1_EN_Pos) #define CLK_APBCLK_UART0_EN_Pos 16 #define CLK_APBCLK_UART0_EN_Msk (1ul << CLK_APBCLK_UART0_EN_Pos) #define CLK_APBCLK_SPI2_EN_Pos 14 #define CLK_APBCLK_SPI2_EN_Msk (1ul << CLK_APBCLK_SPI2_EN_Pos) #define CLK_APBCLK_SPI1_EN_Pos 13 #define CLK_APBCLK_SPI1_EN_Msk (1ul << CLK_APBCLK_SPI1_EN_Pos) #define CLK_APBCLK_SPI0_EN_Pos 12 #define CLK_APBCLK_SPI0_EN_Msk (1ul << CLK_APBCLK_SPI0_EN_Pos) #define CLK_APBCLK_I2C1_EN_Pos 9 #define CLK_APBCLK_I2C1_EN_Msk (1ul << CLK_APBCLK_I2C1_EN_Pos) #define CLK_APBCLK_I2C0_EN_Pos 8 #define CLK_APBCLK_I2C0_EN_Msk (1ul << CLK_APBCLK_I2C0_EN_Pos) #define CLK_APBCLK_FDIV_EN_Pos 6 #define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos) #define CLK_APBCLK_TMR3_EN_Pos 5 #define CLK_APBCLK_TMR3_EN_Msk (1ul << CLK_APBCLK_TMR3_EN_Pos) #define CLK_APBCLK_TMR2_EN_Pos 4 #define CLK_APBCLK_TMR2_EN_Msk (1ul << CLK_APBCLK_TMR2_EN_Pos) #define CLK_APBCLK_TMR1_EN_Pos 3 #define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos) #define CLK_APBCLK_TMR0_EN_Pos 2 #define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos) #define CLK_APBCLK_WDT_EN_Pos 0 #define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos) #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7 #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) #define CLK_CLKSTATUS_OSC22M_STB_Pos 4 #define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) #define CLK_CLKSTATUS_IRC22M_STB_Pos 4 #define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) #define CLK_CLKSTATUS_OSC10K_STB_Pos 3 #define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) #define CLK_CLKSTATUS_IRC10K_STB_Pos 3 #define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) #define CLK_CLKSTATUS_PLL_STB_Pos 2 #define CLK_CLKSTATUS_PLL_STB_Msk (1ul << CLK_CLKSTATUS_PLL_STB_Pos) #define CLK_CLKSTATUS_XTL12M_STB_Pos 0 #define CLK_CLKSTATUS_XTL12M_STB_Msk (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) #define CLK_CLKSEL0_STCLK_S_Pos 3 #define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos) #define CLK_CLKSEL0_HCLK_S_Pos 0 #define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos) #define CLK_CLKSEL1_PWM23_S_Pos 30 #define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos) #define CLK_CLKSEL1_PWM01_S_Pos 28 #define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos) #define CLK_CLKSEL1_UART_S_Pos 24 #define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos) #define CLK_CLKSEL1_TMR3_S_Pos 20 #define CLK_CLKSEL1_TMR3_S_Msk (7ul << CLK_CLKSEL1_TMR3_S_Pos) #define CLK_CLKSEL1_TMR2_S_Pos 16 #define CLK_CLKSEL1_TMR2_S_Msk (7ul << CLK_CLKSEL1_TMR2_S_Pos) #define CLK_CLKSEL1_TMR1_S_Pos 12 #define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos) #define CLK_CLKSEL1_TMR0_S_Pos 8 #define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos) #define CLK_CLKSEL1_SPI2_S_Pos 6 #define CLK_CLKSEL1_SPI2_S_Msk (1ul << CLK_CLKSEL1_SPI2_S_Pos) #define CLK_CLKSEL1_SPI1_S_Pos 5 #define CLK_CLKSEL1_SPI1_S_Msk (1ul << CLK_CLKSEL1_SPI1_S_Pos) #define CLK_CLKSEL1_SPI0_S_Pos 4 #define CLK_CLKSEL1_SPI0_S_Msk (1ul << CLK_CLKSEL1_SPI0_S_Pos) #define CLK_CLKSEL1_ADC_S_Pos 2 #define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos) #define CLK_CLKSEL1_WDT_S_Pos 0 #define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos) #define CLK_CLKSEL2_WWDT_S_Pos 16 #define CLK_CLKSEL2_WWDT_S_Msk (3ul << CLK_CLKSEL2_WWDT_S_Pos) #define CLK_CLKSEL2_PWM23_S_E_Pos 9 #define CLK_CLKSEL2_PWM23_S_E_Msk (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) #define CLK_CLKSEL2_PWM23_S_EXT_Pos 9 #define CLK_CLKSEL2_PWM23_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) #define CLK_CLKSEL2_PWM01_S_E_Pos 8 #define CLK_CLKSEL2_PWM01_S_E_Msk (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) #define CLK_CLKSEL2_PWM01_S_EXT_Pos 8 #define CLK_CLKSEL2_PWM01_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) #define CLK_CLKSEL2_FRQDIV_S_Pos 2 #define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) #define CLK_CLKSEL2_I2S_S_Pos 0 #define CLK_CLKSEL2_I2S_S_Msk (3ul << CLK_CLKSEL2_I2S_S_Pos) #define CLK_CLKDIV_ADC_N_Pos 16 #define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos) #define CLK_CLKDIV_UART_N_Pos 8 #define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos) #define CLK_CLKDIV_USB_N_Pos 4 #define CLK_CLKDIV_USB_N_Msk (0xFul << CLK_CLKDIV_USB_N_Pos) #define CLK_CLKDIV_HCLK_N_Pos 0 #define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos) #define CLK_PLLCON_PLL_SRC_Pos 19 #define CLK_PLLCON_PLL_SRC_Msk (1ul << CLK_PLLCON_PLL_SRC_Pos) #define CLK_PLLCON_OE_Pos 18 #define CLK_PLLCON_OE_Msk (1ul << CLK_PLLCON_OE_Pos) #define CLK_PLLCON_BP_Pos 17 #define CLK_PLLCON_BP_Msk (1ul << CLK_PLLCON_BP_Pos) #define CLK_PLLCON_PD_Pos 16 #define CLK_PLLCON_PD_Msk (1ul << CLK_PLLCON_PD_Pos) #define CLK_PLLCON_OUT_DV_Pos 14 #define CLK_PLLCON_OUT_DV_Msk (3ul << CLK_PLLCON_OUT_DV_Pos) #define CLK_PLLCON_IN_DV_Pos 9 #define CLK_PLLCON_IN_DV_Msk (0x1Ful << CLK_PLLCON_IN_DV_Pos) #define CLK_PLLCON_FB_DV_Pos 0 #define CLK_PLLCON_FB_DV_Msk (0x1FFul << CLK_PLLCON_FB_DV_Pos) #define CLK_FRQDIV_DIVIDER_EN_Pos 4 #define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) #define CLK_FRQDIV_FSEL_Pos 0 #define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos) #define CLK_APBDIV_APBDIV_Pos 0 #define CLK_APBDIV_APBDIV_Msk (1ul << CLK_APBDIV_APBDIV_Pos) Detailed Description Macro Definition Documentation #define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos) CLK_T::AHBCLK: ISP_EN Mask Definition at line of file NUC123.h. #define CLK_AHBCLK_ISP_EN_Pos 2 CLK_T::AHBCLK: ISP_EN Position Definition at line of file NUC123.h. #define CLK_AHBCLK_PDMA_EN_Msk (1ul << CLK_AHBCLK_PDMA_EN_Pos) CLK_T::AHBCLK: PDMA_EN Mask Definition at line of file NUC123.h. #define CLK_AHBCLK_PDMA_EN_Pos 1 CLK_T::AHBCLK: PDMA_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos) CLK_T::APBCLK: ADC_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_ADC_EN_Pos 28 CLK_T::APBCLK: ADC_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos) CLK_T::APBCLK: FDIV_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_FDIV_EN_Pos 6 CLK_T::APBCLK: FDIV_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_I2C0_EN_Msk (1ul << CLK_APBCLK_I2C0_EN_Pos) CLK_T::APBCLK: I2C0_EN_ Mask Definition at line of file NUC123.h. #define CLK_APBCLK_I2C0_EN_Pos 8 CLK_T::APBCLK: I2C0_EN_ Position Definition at line of file NUC123.h. #define CLK_APBCLK_I2C1_EN_Msk (1ul << CLK_APBCLK_I2C1_EN_Pos) CLK_T::APBCLK: I2C1_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_I2C1_EN_Pos 9 CLK_T::APBCLK: I2C1_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_I2S_EN_Msk (1ul << CLK_APBCLK_I2S_EN_Pos) CLK_T::APBCLK: I2S_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_I2S_EN_Pos 29 CLK_T::APBCLK: I2S_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_PS2_EN_Msk (1ul << CLK_APBCLK_PS2_EN_Pos) CLK_T::APBCLK: PS2_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_PS2_EN_Pos 31 CLK_T::APBCLK: PS2_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos) CLK_T::APBCLK: PWM01_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_PWM01_EN_Pos 20 CLK_T::APBCLK: PWM01_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos) CLK_T::APBCLK: PWM23_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_PWM23_EN_Pos 21 CLK_T::APBCLK: PWM23_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_SPI0_EN_Msk (1ul << CLK_APBCLK_SPI0_EN_Pos) CLK_T::APBCLK: SPI0_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_SPI0_EN_Pos 12 CLK_T::APBCLK: SPI0_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_SPI1_EN_Msk (1ul << CLK_APBCLK_SPI1_EN_Pos) CLK_T::APBCLK: SPI1_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_SPI1_EN_Pos 13 CLK_T::APBCLK: SPI1_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_SPI2_EN_Msk (1ul << CLK_APBCLK_SPI2_EN_Pos) CLK_T::APBCLK: SPI2_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_SPI2_EN_Pos 14 CLK_T::APBCLK: SPI2_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos) CLK_T::APBCLK: TMR0_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_TMR0_EN_Pos 2 CLK_T::APBCLK: TMR0_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos) CLK_T::APBCLK: TMR1_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_TMR1_EN_Pos 3 CLK_T::APBCLK: TMR1_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_TMR2_EN_Msk (1ul << CLK_APBCLK_TMR2_EN_Pos) CLK_T::APBCLK: TMR2_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_TMR2_EN_Pos 4 CLK_T::APBCLK: TMR2_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_TMR3_EN_Msk (1ul << CLK_APBCLK_TMR3_EN_Pos) CLK_T::APBCLK: TMR3_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_TMR3_EN_Pos 5 CLK_T::APBCLK: TMR3_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_UART0_EN_Msk (1ul << CLK_APBCLK_UART0_EN_Pos) CLK_T::APBCLK: UART0_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_UART0_EN_Pos 16 CLK_T::APBCLK: UART0_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_UART1_EN_Msk (1ul << CLK_APBCLK_UART1_EN_Pos) CLK_T::APBCLK: UART1_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_UART1_EN_Pos 17 CLK_T::APBCLK: UART1_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_USBD_EN_Msk (1ul << CLK_APBCLK_USBD_EN_Pos) CLK_T::APBCLK: USBD_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_USBD_EN_Pos 27 CLK_T::APBCLK: USBD_EN Position Definition at line of file NUC123.h. #define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos) CLK_T::APBCLK: WDT_EN Mask Definition at line of file NUC123.h. #define CLK_APBCLK_WDT_EN_Pos 0 CLK_T::APBCLK: WDT_EN Position Definition at line of file NUC123.h. #define CLK_APBDIV_APBDIV_Msk (1ul << CLK_APBDIV_APBDIV_Pos) CLK_T::APBDIV: APBDIV Mask Definition at line of file NUC123.h. #define CLK_APBDIV_APBDIV_Pos 0 CLK_T::APBDIV: APBDIV Position Definition at line of file NUC123.h. #define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos) CLK_T::CLKDIV: ADC_N Mask Definition at line of file NUC123.h. #define CLK_CLKDIV_ADC_N_Pos 16 CLK_T::CLKDIV: ADC_N Position Definition at line of file NUC123.h. #define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos) CLK_T::CLKDIV: HCLK_N Mask Definition at line of file NUC123.h. #define CLK_CLKDIV_HCLK_N_Pos 0 CLK_T::CLKDIV: HCLK_N Position Definition at line of file NUC123.h. #define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos) CLK_T::CLKDIV: UART_N Mask Definition at line of file NUC123.h. #define CLK_CLKDIV_UART_N_Pos 8 CLK_T::CLKDIV: UART_N Position Definition at line of file NUC123.h. #define CLK_CLKDIV_USB_N_Msk (0xFul << CLK_CLKDIV_USB_N_Pos) CLK_T::CLKDIV: USB_N Mask Definition at line of file NUC123.h. #define CLK_CLKDIV_USB_N_Pos 4 CLK_T::CLKDIV: USB_N Position Definition at line of file NUC123.h. #define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos) CLK_T::CLKSEL0: HCLK_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL0_HCLK_S_Pos 0 CLK_T::CLKSEL0: HCLK_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos) CLK_T::CLKSEL0: STCLK_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL0_STCLK_S_Pos 3 CLK_T::CLKSEL0: STCLK_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos) CLK_T::CLKSEL1: ADC_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_ADC_S_Pos 2 CLK_T::CLKSEL1: ADC_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos) CLK_T::CLKSEL1: PWM01_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_PWM01_S_Pos 28 CLK_T::CLKSEL1: PWM01_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos) CLK_T::CLKSEL1: PWM23_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_PWM23_S_Pos 30 CLK_T::CLKSEL1: PWM23_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI0_S_Msk (1ul << CLK_CLKSEL1_SPI0_S_Pos) CLK_T::CLKSEL1: SPI0_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI0_S_Pos 4 CLK_T::CLKSEL1: SPI0_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI1_S_Msk (1ul << CLK_CLKSEL1_SPI1_S_Pos) CLK_T::CLKSEL1: SPI1_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI1_S_Pos 5 CLK_T::CLKSEL1: SPI1_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI2_S_Msk (1ul << CLK_CLKSEL1_SPI2_S_Pos) CLK_T::CLKSEL1: SPI2_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_SPI2_S_Pos 6 CLK_T::CLKSEL1: SPI2_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos) CLK_T::CLKSEL1: TMR0_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR0_S_Pos 8 CLK_T::CLKSEL1: TMR0_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos) CLK_T::CLKSEL1: TMR1_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR1_S_Pos 12 CLK_T::CLKSEL1: TMR1_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR2_S_Msk (7ul << CLK_CLKSEL1_TMR2_S_Pos) CLK_T::CLKSEL1: TMR2_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR2_S_Pos 16 CLK_T::CLKSEL1: TMR2_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR3_S_Msk (7ul << CLK_CLKSEL1_TMR3_S_Pos) CLK_T::CLKSEL1: TMR3_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_TMR3_S_Pos 20 CLK_T::CLKSEL1: TMR3_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos) CLK_T::CLKSEL1: UART_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_UART_S_Pos 24 CLK_T::CLKSEL1: UART_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos) CLK_T::CLKSEL1: WDT_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL1_WDT_S_Pos 0 CLK_T::CLKSEL1: WDT_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) CLK_T::CLKSEL2: FRQDIV_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_FRQDIV_S_Pos 2 CLK_T::CLKSEL2: FRQDIV_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_I2S_S_Msk (3ul << CLK_CLKSEL2_I2S_S_Pos) CLK_T::CLKSEL2: I2S_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_I2S_S_Pos 0 CLK_T::CLKSEL2: I2S_S Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM01_S_E_Msk (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) CLK_T::CLKSEL2: PWM01_S_E Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM01_S_E_Pos 8 CLK_T::CLKSEL2: PWM01_S_E Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM01_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) CLK_T::CLKSEL2: PWM01_S_EXT Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM01_S_EXT_Pos 8 CLK_T::CLKSEL2: PWM01_S_EXT Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM23_S_E_Msk (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) CLK_T::CLKSEL2: PWM23_S_E Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM23_S_E_Pos 9 CLK_T::CLKSEL2: PWM23_S_E Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM23_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) CLK_T::CLKSEL2: PWM23_S_EXT Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_PWM23_S_EXT_Pos 9 CLK_T::CLKSEL2: PWM23_S_EXT Position Definition at line of file NUC123.h. #define CLK_CLKSEL2_WWDT_S_Msk (3ul << CLK_CLKSEL2_WWDT_S_Pos) CLK_T::CLKSEL2: WWDT_S Mask Definition at line of file NUC123.h. #define CLK_CLKSEL2_WWDT_S_Pos 16 CLK_T::CLKSEL2: WWDT_S Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) CLK_T::CLKSTATUS: CLK_SW_FAIL Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7 CLK_T::CLKSTATUS: CLK_SW_FAIL Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) CLK_T::CLKSTATUS: IRC10K_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_IRC10K_STB_Pos 3 CLK_T::CLKSTATUS: IRC10K_STB Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) CLK_T::CLKSTATUS: IRC22M_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_IRC22M_STB_Pos 4 CLK_T::CLKSTATUS: IRC22M_STB Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) CLK_T::CLKSTATUS: OSC10K_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_OSC10K_STB_Pos 3 CLK_T::CLKSTATUS: OSC10K_STB Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) CLK_T::CLKSTATUS: OSC22M_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_OSC22M_STB_Pos 4 CLK_T::CLKSTATUS: OSC22M_STB Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_PLL_STB_Msk (1ul << CLK_CLKSTATUS_PLL_STB_Pos) CLK_T::CLKSTATUS: PLL_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_PLL_STB_Pos 2 CLK_T::CLKSTATUS: PLL_STB Position Definition at line of file NUC123.h. #define CLK_CLKSTATUS_XTL12M_STB_Msk (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) CLK_T::CLKSTATUS: XTL12M_STB Mask Definition at line of file NUC123.h. #define CLK_CLKSTATUS_XTL12M_STB_Pos 0 CLK_T::CLKSTATUS: XTL12M_STB Position Definition at line of file NUC123.h. #define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) CLK_T::FRQDIV: DIVIDER_EN Mask Definition at line of file NUC123.h. #define CLK_FRQDIV_DIVIDER_EN_Pos 4 CLK_T::FRQDIV: DIVIDER_EN Position Definition at line of file NUC123.h. #define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos) CLK_T::FRQDIV: FRQDIV_FSEL Mask Definition at line of file NUC123.h. #define CLK_FRQDIV_FSEL_Pos 0 CLK_T::FRQDIV: FRQDIV_FSEL Position Definition at line of file NUC123.h. #define CLK_PLLCON_BP_Msk (1ul << CLK_PLLCON_BP_Pos) CLK_T::PLLCON: OE Mask Definition at line of file NUC123.h. #define CLK_PLLCON_BP_Pos 17 CLK_T::PLLCON: OE Position Definition at line of file NUC123.h. #define CLK_PLLCON_FB_DV_Msk (0x1FFul << CLK_PLLCON_FB_DV_Pos) CLK_T::PLLCON: FB_DV Mask Definition at line of file NUC123.h. #define CLK_PLLCON_FB_DV_Pos 0 CLK_T::PLLCON: FB_DV Position Definition at line of file NUC123.h. #define CLK_PLLCON_IN_DV_Msk (0x1Ful << CLK_PLLCON_IN_DV_Pos) CLK_T::PLLCON: IN_DV Mask Definition at line of file NUC123.h. #define CLK_PLLCON_IN_DV_Pos 9 CLK_T::PLLCON: IN_DV Position Definition at line of file NUC123.h. #define CLK_PLLCON_OE_Msk (1ul << CLK_PLLCON_OE_Pos) CLK_T::PLLCON: PLL_SRC Mask Definition at line of file NUC123.h. #define CLK_PLLCON_OE_Pos 18 CLK_T::PLLCON: PLL_SRC Position Definition at line of file NUC123.h. #define CLK_PLLCON_OUT_DV_Msk (3ul << CLK_PLLCON_OUT_DV_Pos) CLK_T::PLLCON: OUT_DV Mask Definition at line of file NUC123.h. #define CLK_PLLCON_OUT_DV_Pos 14 CLK_T::PLLCON: OUT_DV Position Definition at line of file NUC123.h. #define CLK_PLLCON_PD_Msk (1ul << CLK_PLLCON_PD_Pos) CLK_T::PLLCON: PD Mask Definition at line of file NUC123.h. #define CLK_PLLCON_PD_Pos 16 CLK_T::PLLCON: PD Position Definition at line of file NUC123.h. #define CLK_PLLCON_PLL_SRC_Msk (1ul << CLK_PLLCON_PLL_SRC_Pos) CLK_T::PLLCON: PLL_SRC Mask Definition at line of file NUC123.h. #define CLK_PLLCON_PLL_SRC_Pos 19 CLK_T::PLLCON: PLL_SRC Position Definition at line of file NUC123.h. #define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_IRC10K_EN_Pos) CLK_T::PWRCON: IRC10K_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_IRC10K_EN_Pos 3 CLK_T::PWRCON: IRC10K_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_IRC22M_EN_Pos) CLK_T::PWRCON: IRC22M_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_IRC22M_EN_Pos 2 CLK_T::PWRCON: IRC22M_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) CLK_T::PWRCON: OSC10K_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_OSC10K_EN_Pos 3 CLK_T::PWRCON: OSC10K_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) CLK_T::PWRCON: OSC22M_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_OSC22M_EN_Pos 2 CLK_T::PWRCON: OSC22M_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WAIT_CPU_Msk (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) CLK_T::PWRCON: PD_WAIT_CPU Mask Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WAIT_CPU_Pos 8 CLK_T::PWRCON: PD_WAIT_CPU Position Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_DLY_Msk (1ul << CLK_PWRCON_PD_WU_DLY_Pos) CLK_T::PWRCON: PD_WU_DLY Mask Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_DLY_Pos 4 CLK_T::PWRCON: PD_WU_DLY Position Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_INT_EN_Msk (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) CLK_T::PWRCON: PD_WU_INT_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_INT_EN_Pos 5 CLK_T::PWRCON: PD_WU_INT_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos) CLK_T::PWRCON: PD_WU_STS Mask Definition at line of file NUC123.h. #define CLK_PWRCON_PD_WU_STS_Pos 6 CLK_T::PWRCON: PD_WU_STS Position Definition at line of file NUC123.h. #define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) CLK_T::PWRCON: PWR_DOWN_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_PWR_DOWN_EN_Pos 7 CLK_T::PWRCON: PWR_DOWN_EN Position Definition at line of file NUC123.h. #define CLK_PWRCON_XTL12M_EN_Msk (1ul << CLK_PWRCON_XTL12M_EN_Pos) CLK_T::PWRCON: XTL12M_EN Mask Definition at line of file NUC123.h. #define CLK_PWRCON_XTL12M_EN_Pos 0 CLK_T::PWRCON: XTL12M_EN Position Definition at line of file NUC123.h.
CLK_T Struct Reference
#include <NUC123.h>
Data Fields |
|
| __IO uint32_t | PWRCON |
| __IO uint32_t | AHBCLK |
| __IO uint32_t | APBCLK |
| __IO uint32_t | CLKSTATUS |
| __IO uint32_t | CLKSEL0 |
| __IO uint32_t | CLKSEL1 |
| __IO uint32_t | CLKDIV |
| __IO uint32_t | CLKSEL2 |
| __IO uint32_t | PLLCON |
| __IO uint32_t | FRQDIV |
| __I uint32_t | RESERVE0 |
| __IO uint32_t | APBDIV |
Detailed Description
Field Documentation
| CLK_T::AHBCLK |
Offset: 0x04 AHB Devices Clock Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [1] | PDMA_EN | PDMA Controller Clock Enable Control 0 = PDMA peripheral clock Disabled. 1 = PDMA peripheral clock Enabled. |
| [2] | ISP_EN | Flash ISP Controller Clock Enable Control 0 = Flash ISP peripheral clock Disabled. 1 = Flash ISP peripheral clock Enabled. |
| CLK_T::APBCLK |
Offset: 0x08 APB Devices Clock Enable Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | WDT_EN | Watchdog Timer Clock Enable Control (Write Protect) 0 = Watchdog Timer clock Disabled. 1 = Watchdog Timer clock Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [2] | TMR0_EN | Timer0 Clock Enable Control 0 = Timer0 clock Disabled. 1 = Timer0 clock Enabled. |
| [3] | TMR1_EN | Timer1 Clock Enable Control 0 = Timer1 clock Disabled. 1 = Timer1 clock Enabled. |
| [4] | TMR2_EN | Timer2 Clock Enable Control 0 = Timer2 clock Disabled. 1 = Timer2 clock Enabled. |
| [5] | TMR3_EN | Timer3 Clock Enable Control 0 = Timer3 clock Disabled. 1 = Timer3 clock Enabled. |
| [6] | FDIV_EN | Frequency Divider Output Clock Enable Control 0 = FDIV clock Disabled. 1 = FDIV clock Enabled. |
| [8] | I2C0_EN | I2C0 Clock Enable Control 0 = I2C0 clock Disabled. 1 = I2C0 clock Enabled. |
| [9] | I2C1_EN | I2C1 Clock Enable Control 0 = I2C1 clock Disabled. 1 = I2C1 clock Enabled. |
| [12] | SPI0_EN | SPI0 Clock Enable Control 0 = SPI0 clock Disabled. 1 = SPI0 clock Enabled. |
| [13] | SPI1_EN | SPI1 Clock Enable Control 0 = SPI1 clock Disabled. 1 = SPI1 clock Enabled. |
| [14] | SPI2_EN | SPI2 Clock Enable Control 0 = SPI2 clock Disabled. 1 = SPI2 clock Enabled. |
| [16] | UART0_EN | UART0 Clock Enable Control 0 = UART0 clock Disabled. 1 = UART0 clock Enabled. |
| [17] | UART1_EN | UART1 Clock Enable Control 0 = UART1 clock Disabled. 1 = UART1 clock Enabled. |
| [20] | PWM01_EN | PWM_01 Clock Enable Control 0 = PWM01 clock Disabled. 1 = PWM01 clock Enabled. |
| [21] | PWM23_EN | PWM_23 Clock Enable Control 0 = PWM23 clock Disabled. 1 = PWM23 clock Enabled. |
| [27] | USBD_EN | USB 2.0 FS Device Controller Clock Enable Control 0 = USB clock Disabled. 1 = USB clock Enabled. |
| [28] | ADC_EN | Analog-Digital-Converter (ADC) Clock Enable Control 0 = ADC clock Disabled. 1 = ADC clock Enabled. |
| [29] | I2S_EN | I2S Clock Enable Control 0 = I2S clock Disabled. 1 = I2S clock Enabled. |
| [31] | PS2_EN | PS/2 Clock Enable Control 0 = PS/2 clock Disabled. 1 = PS/2 clock Enabled. |
| CLK_T::APBDIV |
| CLK_T::CLKDIV |
Offset: 0x18 Clock Divider Number Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | HCLK_N | HCLK Clock Divide Number From HCLK Clock Source HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1). |
| [7:4] | USB_N | USB Clock Divide Number From PLL Clock USB clock frequency = (PLL frequency) / (USB_N + 1). |
| [11:8] | UART_N | UART Clock Divide Number From UART Clock Source UART clock frequency = (UART clock source frequency) / (UART_N + 1). |
| [23:16] | ADC_N | ADC Clock Divide Number From ADC Clock Source ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1). |
| CLK_T::CLKSEL0 |
Offset: 0x10 Clock Source Select Control Register 0
| Bits | Field | Descriptions |
|---|---|---|
| [2:0] | HCLK_S | HCLK Clock Source Select (Write Protect) The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. 000 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 001 = Clock source from PLL/2 clock. 010 = Clock source from PLL clock. 011 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on. Note2: These bits are write protected bit. Refer to the REGWRPROT register. |
| [5:3] | STCLK_S | Cortex-M0 SysTick Clock Source Select (Write Protect) If SYST_CSR[2] = 1, SysTick clock source is from HCLK. If SYST_CSR[2] = 0, SysTick clock source is defined by STCLK_S(CLKSEL0[5:3]). 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from external 4~24 MHz high speed crystal clock/2. 011 = Clock source from HCLK/2. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock/2. Note1: If SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2. Note2: These bits are write protected bit. Refer to the REGWRPROT register. |
| CLK_T::CLKSEL1 |
Offset: 0x14 Clock Source Select Control Register 1
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | WDT_S | Watchdog Timer Clock Source Select (Write Protect) 10 = Clock source from HCLK/2048 clock. 11 = Clock source from internal 10 kHz low speed oscillator clock. Note: These bits are write protected bit. Refer to the REGWRPROT register. |
| [3:2] | ADC_S | ADC Clock Source Select 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. |
| [4] | SPI0_S | SPI0 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK. |
| [5] | SPI1_S | SPI1 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK. |
| [6] | SPI2_S | SPI2 Clock Source Selection 0 = Clock source from PLL clock. 1 = Clock source from HCLK. |
| [10:8] | TMR0_S | TIMER0 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved. |
| [14:12] | TMR1_S | TIMER1 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved. |
| [18:16] | TMR2_S | TIMER2 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Clock source from external trigger. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved. |
| [22:20] | TMR3_S | TIMER3 Clock Source Selection 000 = Clock source from external 4~24 MHz high speed crystal clock. 010 = Clock source from HCLK. 011 = Reserved. 101 = Clock source from internal 10 kHz low speed oscillator clock. 111 = Clock source from internal 22.1184 MHz high speed oscillator clock. Others = Reserved. |
| [25:24] | UART_S | UART Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. |
| [29:28] | PWM01_S | PWM0 and PWM1 Clock Source Selection PWM0 and PWM1 used the same clock source; both of them used the same prescaler. The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock. |
| [31:30] | PWM23_S | PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 used the same clock source; both of them used the same prescaler. The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). If PWM23_S_E = 0, theclock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock. |
| CLK_T::CLKSEL2 |
Offset: 0x1C Clock Source Select Control Register 2
| Bits | Field | Descriptions |
|---|---|---|
| [1:0] | I2S_S | I2S Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 01 = Clock source from PLL clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. |
| [3:2] | FRQDIV_S | Clock Divider Clock Source Selection 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. |
| [8] | PWM01_S_E | PWM0 and PWM1 Clock Source Selection Extend PWM0 and PWM1 used the same clock source; both of them used the same prescaler. The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]). If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock. |
| [9] | PWM23_S_E | PWM2 and PWM3 Clock Source Selection Extend PWM2 and PWM3 used the same clock source; both of them used the same prescaler. The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]). If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Clock source from external 4~24 MHz high speed crystal oscillator clock. 10 = Clock source from HCLK. 11 = Clock source from internal 22.1184 MHz high speed oscillator clock. If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below: 00 = Reserved. 01 = Reserved. 10 = Reserved. 11 = Clock source from internal 10 kHz low speed oscillator clock. |
| [17:16] | WWDT_S | Window Watchdog Timer Clock Source Selection 10 = Clock source from HCLK/2048 clock. 11 = Clock source from internal 10 kHz low speed oscillator clock. |
| CLK_T::CLKSTATUS |
Offset: 0x0C Clock status monitor Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | XTL12M_STB | External 4~24 MHz High Speed Crystal (HXT) Clock Source Stable Flag (Read Only) 0 = External 4~24 MHz high speed crystal clock (HXT) is not stable or disabled. 1 = External 4~24 MHz high speed crystal clock (HXT) is stable and enabled. |
| [2] | PLL_STB | Internal PLL Clock Source Stable Flag (Read Only) 0 = Internal PLL clock is not stable or disabled. 1 = Internal PLL clock is stable in normal mode. |
| [3] | OSC10K_STB | Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only) 0 = Internal 10 kHz low speed oscillator clock (LIRC) is not stable or disabled. 1 = Internal 10 kHz low speed oscillator clock (LIRC) is stable and enabled. |
| [4] | OSC22M_STB | Internal 22.1184 MHz High Speed Oscillator (HIRC) Clock Source Stable Flag (Read Only) 0 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is not stable or disabled. 1 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is stable and enabled. |
| [7] | CLK_SW_FAIL | Clock Switching Fail Flag This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1. 0 = Clock switching success. 1 = Clock switching failure. Note1: On NUC123xxxANx, this bit can be cleared to 0 by software writing "1". Note2: On NUC123xxxAEx, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SW_FAIL will be cleared automatically by hardware. |
| CLK_T::FRQDIV |
Offset: 0x24 Frequency Divider Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [3:0] | FSEL | Divider Output Frequency Selection Bits The formula of output frequency is Fout = Fin/2(N+1). Fin is the input clock frequency. Fout is the frequency of divider output clock. N is the 4-bit value of FSEL[3:0]. |
| [4] | DIVIDER_EN | Frequency Divider Enable Bit 0 = Frequency Divider function Disabled. 1 = Frequency Divider function Enabled. |
| CLK_T::PLLCON |
Offset: 0x20 PLL Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [8:0] | FB_DV | PLL Feedback Divider Control Bits Refer to the PLL formulas. |
| [13:9] | IN_DV | PLL Input Divider Control Bits Refer to the PLL formulas. |
| [15:14] | OUT_DV | PLL Output Divider Control Bits Refer to the PLL formulas. |
| [16] | PD | Power-down Mode If the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too. 0 = PLL is in Normal mode. 1 = PLL is in Power-down mode (default). |
| [17] | BP | PLL Bypass Control 0 = PLL is in Normal mode (default). 1 = PLL clock output is same as PLL source clock input. |
| [18] | OE | PLL OE (FOUT Enable) Control 0 = PLL FOUT Enabled. 1 = PLL FOUT is fixed low. |
| [19] | PLL_SRC | PLL Source Clock Selection 0 = PLL source clock from external 4~24 MHz high speed crystal. 1 = PLL source clock from internal 22.1184 MHz high speed oscillator. |
| CLK_T::PWRCON |
Offset: 0x00 System Power-down Control Register
| Bits | Field | Descriptions |
|---|---|---|
| [0] | XTL12M_EN | External 4~24 MHz High Speed Crystal Enable (HXT) Control (Write Protect) The bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]). When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically. 0 = External 4~24 MHz high speed crystal oscillator (HXT) Disabled. 1 = External 4~24 MHz high speed crystal oscillator (HXT) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [2] | OSC22M_EN | Internal 22.1184 MHz High Speed Oscillator (HIRC) Enable Control (Write Protect) 0 = Internal 22.1184 MHz high speed oscillator (HIRC) Disabled. 1 = Internal 22.1184 MHz high speed oscillator (HIRC) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [3] | OSC10K_EN | Internal 10 KHz Low Speed Oscillator (LIRC) Enable Control (Write Protect) 0 = Internal 10 kHz low speed oscillator (LIRC) Disabled. 1 = Internal 10 kHz low speed oscillator (LIRC) Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [4] | PD_WU_DLY | Wake-up Delay Counter Enable Control (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator. 0 = Clock cycles delay Disabled. 1 = Clock cycles delay Enabled. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [5] | PD_WU_INT_EN | Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect) 0 = Power-down mode wake-up interrupt Disabled. 1 = Power-down mode wake-up interrupt Enabled. Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high. Note2: This bit is write protected bit. Refer to the REGWRPROT register. |
| [6] | PD_WU_STS | Power-down Mode Wake-Up Interrupt Status Set by "Power-down wake-up event", it indicates that resume from Power-down mode. The flag is set if the GPIO, USB, UART, WDT, TIMER, I2C or BOD wake-up occurred. This bit can be cleared to 0 by software writing "1". Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1. |
| [7] | PWR_DOWN_EN | System Power-down Enable Bit (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit (a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend) When chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down. In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed RC oscillator (HIRC) will be disabled in this mode, but the 10 kHz internal low speed RC oscillator (LIRC) is not controlled by Power-down mode. In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the 10 kHz internal low speed RC oscillator (LIRC). The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator. 0 = Chip operating normally or chip in Idle mode because of WFI command. 1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
| [8] | PD_WAIT_CPU | This Bit Control The Power-Down Entry Condition (Write Protect) 0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1. 1 = Chip enters Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction. Note: This bit is write protected bit. Refer to the REGWRPROT register. |
The documentation for this struct was generated from the following file:
D:/MCU/FA8248/NUC123BSPv3/Library/Device/Nuvoton/NUC123/Include/NUC123.h
/**************************************************************************//**
* @file mainS.c
* @version V2.00
* $Revision: 4 $
* $Date: 14/01/28 11:44a $
* @brief NUC029 Series Global Control and Clock Control Driver Sample Code
*
* @note
* Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NUC029xAN.h" #define PLLCON_SETTING CLK_PLLCON_50MHz_HXT
#define PLL_CLOCK 50000000 #define SIGNATURE 0x125ab234
#define FLAG_ADDR 0x20000FFC /*---------------------------------------------------------------------------------------------------------*/
/* Brown Out Detector IRQ Handler */
/*---------------------------------------------------------------------------------------------------------*/
void BOD_IRQHandler(void)
{
/* Clear BOD Interrupt Flag */
SYS_CLEAR_BOD_INT_FLAG(); printf("Brown Out is Detected\n");
} /*---------------------------------------------------------------------------------------------------------*/
/* Simple calculation test function */
/*---------------------------------------------------------------------------------------------------------*/
#define PI_NUM 256
int32_t f[PI_NUM + ];
uint32_t piTbl[] =
{
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
, }; int32_t piResult[]; int32_t pi(void)
{
int32_t i, i32Err;
int32_t a = , b = , c = PI_NUM, d = , e = , g = ; for(; b - c;)
f[b++] = a / ; i = ;
for(; d = , g = c * ; c -= ,/*printf("%.4d\n",e+d/a),*/ piResult[i++] = e + d / a, e = d % a)
{
if(i == )
break; for(b = c; d += f[b] * a, f[b] = d % --g, d /= g--, --b; d *= b);
}
i32Err = ;
for(i = ; i < ; i++)
{
if(piTbl[i] != piResult[i])
i32Err = -;
} return i32Err;
} void Delay(uint32_t x)
{
int32_t i; for(i = ; i < x; i++)
{
__NOP();
__NOP();
}
} uint32_t g_au32PllSetting[] =
{
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 25MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 29MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 33MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 37MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 41MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4, /* PLL = 45MHz */
CLK_PLLCON_PLL_SRC_HXT | CLK_PLLCON_NR() | CLK_PLLCON_NF() | CLK_PLLCON_NO_4 /* PLL = 49MHz */
}; void SYS_PLL_Test(void)
{
int32_t i; /*---------------------------------------------------------------------------------------------------------*/
/* PLL clock configuration test */
/*---------------------------------------------------------------------------------------------------------*/ printf("\n-------------------------[ Test PLL ]-----------------------------\n"); for(i = ; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[]) ; i++)
{
/* Switch HCLK clock source to HXT and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HXT;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk); /* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */
CLK->PLLCON &= ~CLK_PLLCON_PD_Msk; /* Set PLL frequency */
CLK->PLLCON = g_au32PllSetting[i]; /* Waiting for PLL clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk)); /* Switch HCLK clock source to PLL */
CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL; /* Update System Core Clock */
SystemCoreClockUpdate(); printf(" Change system clock to %d Hz ...................... ", SystemCoreClock); /* Enable CKO clock source */
CLK->APBCLK |= CLK_APBCLK_FDIV_EN_Msk; /* CKO = clock source / 2^(1 + 1) */
CLK->FRQDIV = CLK_FRQDIV_DIVIDER_EN_Msk | (); /* Select CKO clock source as HCLK */
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV_S_Msk)) | CLK_CLKSEL2_FRQDIV_S_HCLK; /* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000); if(pi())
{
printf("[FAIL]\n");
}
else
{
printf("[OK]\n");
} /* Disable CKO clock */
CLK->APBCLK &= (~CLK_APBCLK_FDIV_EN_Msk);
}
} void SYS_Init(void)
{ /*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk; /* Waiting for Internal RC clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk)); /* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk); /* Enable external XTAL 12MHz clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk; /* Waiting for external XTAL clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk)); /* Set core clock as PLL_CLOCK from PLL */
CLK->PLLCON = PLLCON_SETTING;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL; /* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / ; // HCLK
CyclesPerUs = PLL_CLOCK / ; // For SYS_SysTickDelay() /* Enable UART module clock */
CLK->APBCLK |= CLK_APBCLK_UART0_EN_Msk; /* Select UART module clock source */
CLK->CLKSEL1 &= ~CLK_CLKSEL1_UART_S_Msk;
CLK->CLKSEL1 |= CLK_CLKSEL1_UART_S_HXT; /*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/ /* Set P3 multi-function pins for UART0 RXD , TXD and CKO */
SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk | SYS_MFP_P36_Msk);
SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0 | SYS_MFP_P36_CKO); } void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART IP */
SYS->IPRSTC2 |= SYS_IPRSTC2_UART0_RST_Msk;
SYS->IPRSTC2 &= ~SYS_IPRSTC2_UART0_RST_Msk; /* Configure UART0 and set UART0 Baudrate */
UART0->BAUD = UART_BAUD_MODE2 | UART_BAUD_MODE2_DIVIDER(__HXT, );
UART0->LCR = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
} /*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data; /* If define INIT_SYSCLK_AT_BOOTING in system_NUC029xAN.h, HCLK will be set to 50MHz in SystemInit(void). */
/* In end of main function, program issued CPU reset and write-protection will be disabled. */
if(SYS->REGWRPROT == )
SYS->REGWRPROT = 0x0; /* Unlock protected registers */
SYS->REGWRPROT = 0x59;
SYS->REGWRPROT = 0x16;
SYS->REGWRPROT = 0x88; /* Init System, IP clock and multi-function I/O */
SYS_Init(); /* Lock protected registers */
SYS->REGWRPROT = 0x0; /* Init UART0 for printf */
UART0_Init(); printf("\n\nCPU @ %dHz\n", SystemCoreClock); /*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Output system clock from CKO pin, and the output frequency = system clock / 4
*/ printf("+---------------------------------------+\n");
printf("| System Driver Sample Code |\n");
printf("+---------------------------------------+\n"); if(M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = ;
printf(" Press any key to continue ...\n");
getchar();
} /*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/ /* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID); /* Get reset source from last operation */
u32data = SYS->RSTSRC;
printf("Reset Source 0x%x\n", u32data); /* Clear reset source */
SYS->RSTSRC = u32data; /* Unlock protected registers for Brown-Out Detector settings */
SYS->REGWRPROT = 0x59;
SYS->REGWRPROT = 0x16;
SYS->REGWRPROT = 0x88; /* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS->REGWRPROT != )
{
printf("Protected Address is Unlocked\n");
} /* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.7V */
SYS->BODCR = SYS_BODCR_BOD_EN_Msk | SYS_BODCR_BOD_VL_2_7V | SYS_BODCR_LVR_EN_Msk; /* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn); /* Run PLL Test */
SYS_PLL_Test(); /* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n"); /* Waiting for message send out */
while(!(UART0->FSR & UART_FSR_TE_FLAG_Msk)); /* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= (CLK_CLKDIV_HCLK() << CLK_CLKDIV_HCLK_N_Msk); /* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
CLK->PLLCON &= ~CLK_PLLCON_PD_Msk; /* Reset CPU */
SYS->IPRSTC1 |= SYS_IPRSTC1_CPU_RST_Msk;
}