A transition between the states only occurs on the rising edge of TCK, and each state has a different name.

The two vertical columns with seven states each represent the Instruction Path and the Data Path.

The data registers operate in the states whose names end with "DR" and

the instruction register operates in the states whose names end in "IR".

The states are otherwise identical.

The operation of each state is described below.

Test-Logic-Reset
All test logic is disabled in this controller state enabling the normal operation of the IC.
The TAP controller state machine is designed so that, no matter what the initial state of the controller is,
the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times.
This is why the Test Reset (TRST) pin is optional.

Run-Test-Idle
In this controller state, the test logic in the IC is active only if certain instructions are present.
For example, if an instruction activates the self test, then it is executed when the controller enters this state.
The test logic in the IC is idle otherwise.

Select-DR-Scan
This controller state controls whether to enter the Data Path or the Select-IR-Scan state.

Select-IR-Scan
This controller state controls whether or not to enter the Instruction Path.
The Controller can return to the Test-Logic-Reset state otherwise.

Capture-IR
In this controller state, the shift register bank in the Instruction Register
parallel loads a pattern of fixed values on the rising edge of TCK.
The last two significant bits must always be "01".

Shift-IR
In this controller state, the instruction register gets connected between TDI and TDO,
and the captured pattern gets shifted on each rising edge of TCK.
The instruction available on the TDI pin is also shifted in to the instruction register.

Exit1-IR
This controller state controls whether to enter the Pause-IR state or Update-IR state.

Pause-IR
This state allows the shifting of the instruction register to be temporarily halted.

Exit2-DR
This controller state controls whether to enter either the Shift-IR state or Update-IR state.

Update-IR
In this controller state, the instruction in the instruction register is
latched to the latch bank of the Instruction Register on every falling edge of TCK.
This instruction becomes the current instruction once it is latched.

Capture-DR
In this controller state, the data is parallel-loaded into the data registers selected
by the current instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR and Update-DR
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR
and Update-IR states in the Instruction path.

Instruction Register

The instruction register (IR) consists of three IR cells.

Each cell has a shift-register stage and a latch stage (Figure 5).

On the Capture-IR state, the shift register is loaded with bits 001,

which are used for fault isolation of the board-level serial test data path.

The TDI-IR-TDO path is established on the Shift-IR state.

Data in the shift register is shifted toward TDO, and data in the latch remains the same.

The data in the shift registers is latched out and becomes the current instruction

on the falling edge of the TCK in the Update-IR state.

When the TAP controller enters the Test-Logic Reset state,

bits 111 are latched in IR, which corresponds to the BYPASS instruction,

and the data in the shift register cell retain their previous values.

Table 2 shows the summary of the operation of the instruction register

Instructions

Table 3 lists the supported instructions with their corresponding IR codes and descriptions.

Bypass Register

The bypass register is a single-bit register that provides a minimum data path between the TDI and TDO pins (Figure 6).

The bypass register is selected when the BYPASS, HIGHZ, or CLAMP instruction is the current instruction in the instruction register.

On the Capture-DR controller state, 0 is loaded into the bypass register.

Test data can then be shifted from the TDI to the TDO pin on the Shift-DR state.

By moving into the Update-DR controller state, data movement through the bypass register is terminated.

Table 4 shows the summary of the operation of the bypass register.

Boundary-Scan Register

The boundary-scan register is used to observe and control the state of each system pin, including the clock pins.

Each boundary-scan cell consists of serial input (SI) and serial output (SO) that are connected to each cell, as shown in Figure 7.

In addition, each cell consists of a parallel input (PI) and a latched parallel output (PO) that connect to the system logic and system output.

Three cells are used for each I/O: an input cell (BS2), an output cell (BS1), and an output-enable cell (BS0).

The operation of the boundary-scan register under specific boundary-scan instruction is illustrated in Tables 5 and 6.

If the EXTEST instruction is not being used in conjunction with the SAMPLE/PRELOAD instruction,

the external test starts by shifting the desired test data into the boundary-scan register in the Shift-DR controller state.

By moving into the Update-DR controller state, data shifting is terminated, and on the falling edge of the TCK,

the data from the shift-register stage is transferred onto the parallel output of the latch stage.

The external test results are loaded into the shift-register stage from the system input on the next Capture-DR controller state

and are examined by shifting the data toward TDO on the next Shift-DR controller state.

During the SAMPLE/PRELOAD instruction, the Shift-DR state is used to shift out the data captured from the system input

and output pins for examination during the Capture-DR state.

At the same time, the Shift-DR state shifts in test data to be used by the next boundary-scan instruction

other than SAMPLE/PRELOAD.

The EXTEST instruction is usually initiated following the SAMPLE/PRELOAD instruction.

The data preloaded during the SAMPLE/PRELOAD instruction phase becomes available at the parallel output of the boundary-scan cells

when the EXTEST becomes the current instruction on the falling edge of TCK in the Update-IR state.

Similarly, the CLAMP instruction is usually initiated following the SAMPLE/PRELOAD instruction.

The latched data in the boundary-scan cell becomes available to the system output pins

when CLAMP becomes the current instruction and when the bypass register is selected as the data path from TDI to TDO.