Logic Bist Arch

一般现在多用的都是offline BIST的架构,可以分为4大类:

1)those assume no special structure to the circuit under test;

2)those that make use of scan chains in the circuit under test;

3)those that configure scan chains for test pattern generation and output reponse analysis;

4)those that use the concurrent checking circuitry of the design;

BIST Archi for circuit without scan design

需要增加的逻辑:two LFSR,two multiplexers,(CSBL arch)

1)第一个multiplexer选择PI或PRPG的输入;

2)CUT是一个或combinational或sequential的circuit;

3)第二个multiplexer选择PO或SISR的输出;

4)SISR比较最终的signature与嵌入的golden signature的区别;

Logic Bist Arch

STUMPS架构:

Logic Bist Arch

CBILBO架构:

Logic Bist Arch

BIST arch for circuit with scan chain

LSSD On-Chip Self-Test

CUT中的scan design的output移动到SISR中,并将pass/fail的error signal给Sout.

Logic Bist Arch

BIST Arch Using Concurrent Checking Circuit

Concurrent Self-Verification(CSV)

Logic Bist Arch

CBILBO是唯一一种可以使用pesudo-exhausting的架构;

CSV是唯一一种不需要额外的SISR或MISR的架构;

STUMPS目前应用最广的架构;但是是使用pseudo-random pattern generation的架构;

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