关于Error (10200): Verilog HDL Conditional Statement error at test.v(43): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct问题

代码1如下：
always @(posedge clk or negedge rst )
begin
if(!rst)
Num<=8’d0;
else
begin
if(Num<8’d255)
Num<=Num+8’d1;

	else
	Num<=8'd0;
end	

end

always @(posedge clk or negedge rst )
begin
if(!rst)
cnt<=4’d0;
else
begin
if(cnt==4’d15)begin
Fre<=~Fre;
cnt<=4’d0;
end
else
cnt<=cnt+4’d1;
end
end

always @(posedge Fre or negedge rst)
begin
if(Fre)
DOUT<=Num;
end
编译正常，仿真波形如下：

代码2如下：
always @(posedge clk or negedge rst )
begin
if(!rst)
Num<=8’d0;
else
begin
if(Num<8’d255)
Num<=Num+8’d1;

	else
	Num<=8'd0;
end	

end

always @(posedge clk or negedge rst )
begin
if(!rst)
cnt<=4’d0;
else
begin
if(cnt==4’d15)begin
Fre<=~Fre;
cnt<=4’d0;
end
else
cnt<=cnt+4’d1;
end
end

always @(negedge Fre or negedge rst)
begin
if(!Fre)
DOUT<=Num;
end
编译正常，仿真波形如下：

代码3如下、
always @(posedge Fre or negedge rst)
begin
if(!Fre)
DOUT<=Num;
end
编译错误；

代码4如下：
always @(negedge Fre or negedge rst)
begin
if(Fre)
DOUT<=Num;
end
编译错误；

触发信号边沿条件需与条件语句对应；