有限状态机的三段式写法.md

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output reg out);//  

    reg ns,cs;

    parameter sa = 1'b1, sb = 1'b0;

    //The clc: generate the ns
    always @(in or cs) begin
        case(cs)
            sb: if (in) ns = sb;
                else     ns = sa;
            sa: if (in) ns = sa;
                else     ns = sb;
            default:     ns = 1'bx;
        endcase
    end

    //The slc: store the ns. ns -> cs.
    always @(posedge clk or posedge areset) begin
        if (areset) begin
            cs <= sb;
        end else begin
            cs <= ns;
        end
    end

    //The clc: generate the output
    always @(cs) begin
        if (cs) begin
            out = 1'b0;
        end else begin
            out = 1'b1;
        end
    end

endmodule