1.VHDL语言

package mtype is                                --定义一个包，包中包含的通用定义可以在整个VHDL或多个设计*享使用。 
type state_t is (s1,s2,s3,s0);
end mtype;

library ieee;
use ieee.std_logic_1164.all;
use work.mtype.all;

entity s4_machine is
    port(clk,inc,al,bl : in std_logic;
	      rst : in boolean;
			out1 : out std_logic);
end s4_machine;

architecture behave of s4_machine is              --在结构体中定义了两个同步运行的进程
signal current_state,next_state : state_t;        --声明两个信号，类型对应包中的类型
begin 
    sync : process(clk,rst)                       --进程sync：监测复位信号rst，一旦测得复位信号，
	 begin                                         --当前状态立即返回到初始态s0
	     if(rst) then  
		      current_state <= s0;
				elsif(clk'event and clk = '1') then   --没有复位信号，就监测时钟信号clk，当clk为上升沿
		  current_state <= next_state;              --当前状态值立即赋给信号current_state，并由他传给第二个进程
		  end if;                                   --在同一时间，第二个进程根据current_state的值，确定下一状态的值
	 end process sync;

    fsm : process(inc,current_state,al,bl)
	 begin
	     out1 <= al;
		  next_state <= s0;
		  if (inc = '1') then
		  case current_state is
		    when s0 => next_state <= s1;
			 when s1 => next_state <= s2;
		  out1 <= bl;
		    when s2 => next_state <= s3;
			 when s3 => null;
		  end case;
		  end if;
	 end process fsm;
end behave;