// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)

`timescale 1ps/1ps

module ad_dcfilter #(

  // data path disable

  parameter   DISABLE = ) (

  // data interface

  input           clk,

  input           valid,

  input   [:]  data,

  output          valid_out,

  output  [:]  data_out,

  // control interface

  input           dcfilt_enb,

  input   [:]  dcfilt_coeff,

  input   [:]  dcfilt_offset);

  // internal registers

  reg     [:]  dcfilt_coeff_d = 'd0;

  reg     [:]  dc_offset = 'd0;

  reg     [:]  dc_offset_d = 'd0;

  reg             valid_d = 'd0;

  reg     [:]  data_d = 'd0;

  reg             valid_2d = 'd0;

  reg     [:]  data_2d = 'd0;

  reg     [:]  data_dcfilt = 'd0;

  reg             valid_int = 'd0;

  reg     [:]  data_int = 'd0;

  // internal signals

  wire    [:]  dc_offset_s;

  // data-path disable

  generate

  if (DISABLE == ) begin

  assign valid_out = valid;

  assign data_out = data;

  end else begin

  assign valid_out = valid_int;

  assign data_out = data_int;

  end

  endgenerate

  // dcfilt_coeff is flopped so to remove warnings from vivado

  always @(posedge clk) begin

    dcfilt_coeff_d <= dcfilt_coeff;

  end

  // removing dc offset

  always @(posedge clk) begin

    dc_offset   <= dc_offset_s;

    dc_offset_d <= dc_offset;

    valid_d <= valid;

    if (valid == 'b1) begin

      data_d <= data + dcfilt_offset;

    end

    valid_2d <= valid_d;

    data_2d  <= data_d;

    data_dcfilt <= data_d - dc_offset[:];

    if (dcfilt_enb == 'b1) begin

      valid_int <= valid_2d;

      data_int  <= data_dcfilt;

    end else begin

      valid_int <= valid_2d;

      data_int  <= data_2d;

    end

  end

  // dsp slice instance ((D-A)*B)+C

  DSP48E1 #(

    .ACASCREG (),

    .ADREG (),

    .ALUMODEREG (),

    .AREG (),

    .AUTORESET_PATDET ("NO_RESET"),

    .A_INPUT ("DIRECT"),

    .BCASCREG (),

    .BREG (),

    .B_INPUT ("DIRECT"),

    .CARRYINREG (),

    .CARRYINSELREG (),

    .CREG (),

    .DREG (),

    .INMODEREG (),

    .MASK ('h3fffffffffff),

    .MREG (),

    .OPMODEREG (),

    .PATTERN ('h000000000000),

    .PREG (),

    .SEL_MASK ("MASK"),

    .SEL_PATTERN ("PATTERN"),

    .USE_DPORT ("TRUE"),

    .USE_MULT ("MULTIPLY"),

    .USE_PATTERN_DETECT ("NO_PATDET"),

    .USE_SIMD ("ONE48"))

  i_dsp48e1 (

    .CLK (clk),

    .A ({{{dc_offset_s[]}}, dc_offset_s[:]}),

    .B ({{{dcfilt_coeff_d[]}}, dcfilt_coeff_d}),

    .C (dc_offset_d),

    .D ({{{data_d[]}}, data_d}),

    .MULTSIGNIN ('d0),

    .CARRYIN ('d0),

    .CARRYCASCIN ('d0),

    .ACIN ('d0),

    .BCIN ('d0),

    .PCIN ('d0),

    .P (dc_offset_s),

    .MULTSIGNOUT (),

    .CARRYOUT (),

    .CARRYCASCOUT (),

    .ACOUT (),

    .BCOUT (),

    .PCOUT (),

    .ALUMODE ('d0),

    .CARRYINSEL ('d0),

    .INMODE ('b01100),

    .OPMODE ('b0110101),

    .PATTERNBDETECT (),

    .PATTERNDETECT (),

    .OVERFLOW (),

    .UNDERFLOW (),

    .CEA1 ('d0),

    .CEA2 ('d1),

    .CEAD ('d1),

    .CEALUMODE ('d0),

    .CEB1 ('d0),

    .CEB2 ('d1),

    .CEC ('d1),

    .CECARRYIN ('d0),

    .CECTRL ('d0),

    .CED ('d1),

    .CEINMODE ('d0),

    .CEM ('d1),

    .CEP ('d0),

    .RSTA ('d0),

    .RSTALLCARRYIN ('d0),

    .RSTALUMODE ('d0),

    .RSTB ('d0),

    .RSTC ('d0),

    .RSTCTRL ('d0),

    .RSTD ('d0),

    .RSTINMODE ('d0),

    .RSTM ('d0),

    .RSTP ('d0));

endmodule