input [1:0] A,B,C,D;
input[1:0] sel;
output [1:0] dataout;
output ds;
output [6:0] seg7;
reg [1:0]dataout;
reg [6:0] seg7;
assign ds=0;
always @(sel)
case(sel)
2'b00:
begin
dataout<=A;
seg7=7'b0111111;
end
2'b01:
begin
dataout<=B;
seg7=7'b0000110;
end
2'b10:
begin
dataout<=C;
seg7=7'b1011011;
end
2'b11:
begin
dataout<=D;
seg7=7'b1001111;
end
default:
begin
dataout<=A;
seg7=7'b0111111;
end
endcase
endmodule