//--------------------module_counter_ctrl--------------------//

module counter_ctrl (

    input clk_25m,

    input rst_n,

    output fpga_ledg

);

//--------------------counter_ctrl--------------------------//

/*计数器控制绿色led闪烁*/

reg [:]cnt;

reg ledg;

always@(posedge clk_25m or negedge rst_n)

    if(!rst_n)

        begin

            ledg <= 'd1;

            cnt <= 'd0;

        end

    else if(cnt == 'd5000000)

        begin

            ledg <= ~ledg;

            cnt <= 'd0;

        end

    else

        cnt <= cnt + 'd1;

assign fpga_ledg = ledg;

//--------------------endmodule-----------------------------//

endmodule