int main(void)

{

  /* USER CODE BEGIN 1 */

    int i;

    int address,data;

    char error_flag = ;

    char receive_data[];

    char buffer[];

    char *p;

  /* USER CODE END 1 */

  /* MCU Configuration----------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */

  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */

  SystemClock_Config();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */

  MX_GPIO_Init();

  MX_USART6_UART_Init();

  MX_FMC_Init();

  /* USER CODE BEGIN 2 */

    usart6.initialize();

    usart6.printf("Hello, I am iCore4!\r\n");

    LED_GREEN_ON;

  /* USER CODE END 2 */

  /* Infinite loop */

  /* USER CODE BEGIN WHILE */

  while ()

  {

  /* USER CODE END WHILE */

  /* USER CODE BEGIN 3 */

        if(usart6.receive_ok_flag == ){

            usart6.receive_ok_flag = ;

            memset(receive_data,,sizeof(receive_data));

            memset(buffer,,sizeof(buffer));

            for(i = ;i < ;i ++){

                receive_data[i] = usart6.receive_buffer[i];

            }

            p = receive_data;

            i = ;

            while(*p != ':'){                                    //»ñÈ¡²Ù×÷ÃüÁwrite or read£©

                buffer[i++] = *p++;

                if(i > sizeof(buffer))i = ;

            }

            for(i = ;i < sizeof(buffer);i++){//½«ÃüÁîת»¯ÎªÐ¡Ð´×Ö·û

                buffer[i] = tolower(buffer[i]);

            }

            if(memcmp(buffer,"read",strlen("read")) == ){//Ö´ÐжÁ²Ù×÷

                error_flag = ;

                p++;

                address = atoi(p);

                if(address > )error_flag = ;

                p++;

                if(strchr(p,','))error_flag = ;

                if(!error_flag){

                    data = fpga_read(address);

                    usart6.printf("Read FPGA Ram:%d\r\n",data);

                }

            }else{

                error_flag = ;

            }

            if(error_flag){

                LED_RED_ON;

                LED_GREEN_OFF;

                usart6.printf("Bad Command!\r\n");

            }else{

                LED_RED_OFF;

                LED_GREEN_ON;

            }

        }

  }

  /* USER CODE END 3 */

}

module dual_port_ram_ctrl(

    input clk_25m,

    input rst_n,

    input wrn,

    input rdn,

    input cs0,

    inout [:]db,

    input [:]ab,

    output led_red,

    output led_green,

    output led_blue

);

//-----------------------------ram-----------------------------//

wire [:]dataout_a;

wire [:]dataout_b;

ram u1(

    .data_a(data_a),

    .address_a(address_a),

    .wren_a(wren_a),

    .rden_a(rden_a),

    .clock_a(!clk_a),

    .q_a(dataout_a),

    .data_b(db),

    .address_b(ab),

    .wren_b('d0),

    .rden_b(!rd),

    .clock_b(clk_b),

    .q_b(dataout_b)

);

//-----------------------------clk_100m-----------------------------//

pll u2(

    .inclk0(clk_25m),

    .c0(clk_100m)

);

//-------------------------------clk_a-----------------------------//

reg clk1,clk2;

always@(posedge clk_100m or negedge rst_n)

    if(!rst_n)

        begin

            clk1 <= 'd0;

            clk2 <= 'd0;

        end

    else

        {clk2,clk1} <= {clk1,clk_25m};

wire clk_a = (clk_25m & clk1);

//-------------------------------data-----------------------------//

reg [:]data;

always@(posedge clk_25m or negedge rst_n)

    if(!rst_n)

        data <= 'd0;

    else if(data == 'd511)

        data <= 'd0;

    else

        data <= data + 'd1;

//-------------------------write & read port a-------------------//

reg wren_a;

reg rden_a;

reg [:]data_a;

reg [:]address_a;

always@(posedge clk_a or negedge rst_n)

    if(!rst_n)

        begin

            wren_a <= 'd0;

            rden_a <= 'd0;

            data_a <= 'd0;

            address_a <= 'd0;

        end

    else if(data >= 'd0 && data <= 10'd255)

        begin

            wren_a <= 'd1;

            rden_a <= 'd0;

            data_a <= data;

            address_a <= data;

        end

    else if(data >= 'd256 && data <= 10'd511)

        begin

            wren_a <= 'd0;

            rden_a <= 'd1;

            address_a <= data - 'd256;

        end

//-----------------------------ram a---------------------------//

reg error;

always@(negedge clk1 or negedge rst_n)

    if(!rst_n)

            error <= 'd0;

    else

        begin

            if(wren_a || dataout_a == address_a)

                error <= 'd0;

            else

                error <= 'd1;

        end

//--------------------------ram_a_led---------------------------//

reg ledr,ledg,ledb;

always@(posedge error or negedge rst_n)

    if(!rst_n)

        begin

            ledr <= 'd1;

            ledg <= 'd0;

            ledb <= 'd1;

        end

    else

        begin

            ledr <= 'd0;

            ledg <= 'd1;

            ledb <= 'd1;

        end

assign {led_red,led_green,led_blue} = {ledr,ledg,ledb};

//--------------------------ram_b_rd----------------------------//

wire rd = (cs0 | rdn);

wire wr = (cs0 | wrn);

reg wr_clk1,wr_clk2;

always@(posedge clk_100m or negedge rst_n)

    if(!rst_n)

        begin

            wr_clk1 <= 'd1;

            wr_clk2 <= 'd1;

        end

    else

        {wr_clk2,wr_clk1} <= {wr_clk1,wr};

wire clk_b = (!wr_clk2 | !rd);

assign db = !rd ? dataout_b : 'hzzzz;

endmodule