STA LEARN NOTE
目录Static Timing Analysis for Nanometer Designs: A Practical Approach
基础知识部分
transition delay（信号转换延迟）
transition delay指的是输入或输出端口信号H2L或L2H所需时间，
不是通过gate的时间
transition delay parameter（信号转换延迟相关参数）
PARAMETER MEANING slew_lower_threshold_pct_fall 下降沿，低位阈值电压百分比 slew_upper_threshold_pct_fall 下降沿，高位阈值电压百分比 slew_lower_threshold_pct_rise 上升沿，低位阈值电压百分比 slew_upper_threshold_pct_rise 上升沿，高位阈值电压百分比 fall/rise代表端口电平变化趋势，fall H2L，rise L2H
lower/upper代表变化趋势中的高位和地位，以百分比形式表达(10%90%)or(20%80%)
A slew rate is defined as a rate of change. In static timing analysis, the rising or falling waveforms are measured in terms of whether the transition is slow or fast. The slew is typically measured in terms of the transition time, that is, the time it takes for a signal to transition between two specific levels. Note that the transition time is actually inverse of the slew rate - the larger the transition time, the slower the slew, and vice versa. slew rate定义为变化的速率。slew rate通常通过transition time计算，slew rate和transition time呈现出反比的关系，即transition time越大slew rate越小。
propagation delay（逻辑门延迟）
logic gate delay指的是输入信号经过cell后转化为正确的输出端口信号的时间差
logic gate delay parameter（逻辑门延迟相关参数）
PARAMETER MEANING input_threshold_pct_rise 输入端口上升沿百分比 output_threshold_pct_rise 输出端口上升沿百分比 input_threshold_pct_fall 输入端口下降沿百分比 output_threshold_pct_fall 输出端口下降沿百分比 fall/rise代表端口电平变化趋势，fall H2L，rise L2H
propagation delay百分比一般为50%
timing arc（时序弧）
1. positive unate timing arc（同向时序弧） A rising transition on an input causes the output to rise (or not to change) and a falling transition on an input causes the output to fall (or not to change). 2. negtive unate timing arc（反向时序弧） A rising transition on an input causes the output to have a falling transition (or not to change) and a fall-ing transition on an input causes the output to have a rising transition (or not to change). 3. non-unate timing arc（不定态时序弧） The output transition cannot be determined solely from the direction of change of an input but also depends upon the state of the other inputs.
setup/hold time（建立/保持时间）
建立时间：时序cell正常工作，保证功能正确，上升沿到来前数据保持稳定的最小时间
建立时间测量定义：数据信号电压到50 percent时刻与时钟信号电压达到50 percent时刻间的时间差（相较于std voltage）
保持时间：时序cell正常工作，保证功能正确，上升沿到来后数据保持稳定的最小时间
保持时间测量定义：时钟信号电压达到50 percent时刻与数据信号电压到50 percent时刻间的时间差（相较于std voltage）
timing path（时序路径）
timing path指起点和终点间的path
start point:：组合逻辑单元数据输入端口或时序单元clk输入端口
end point：组合逻辑单元数据输出端口或时序单元数据输入端口
TYPE MEANING input to output 组合逻辑单元数据输入端口到组合逻辑单元数据输出端口 input to register 组合逻辑单元数据输入端口到时序逻辑单元数据输入端口 register to output 时序逻辑单元时钟输入端口到组合逻辑单元数据输出端口 register to register 时序逻辑单元时钟输入端口到时序逻辑单元数据输入端口
path delay：信号从start point经过某一路径到达endpoint的总时间称作路径延迟
max timing path（最大时序路径）：The path from start point to endpoint need max timing called max timing path[ longest path ]
min timing path（最小时序路径）：The path form start point to endpoint need min timing called min timing path[ shortest path ]
clock skew（时钟偏斜）
clock skew指两个或多个信号间的时间差值
时钟从时钟源出发在不同时刻到达目的端口，时刻最大与最小的差之就是clock skew
Skew is the difference in timing between two or more signals, maybe data,clock or both. For example, if a clock tree has 500 end points and has a skew of 50ps, it means that the difference in latency between the longest path and the shortest clock path is 50ps.
可以通过以下语句对clock skew进行约束：
set_clock_uncertainty 0.250 -setup [get_clocks BZCLK] set_clock_uncertainty 0.100 -hold [get_clocks BZCLK]
clock jitter（时钟抖动）
clock jitter指的是时钟沿抖动而形成的一个窗口
Every real clock source has a finite amount of jitter - a window within which a clock edge can occur. The clock period jitter is determined by the type of clock generator utilized. In reality, there are no ideal clocks, that is, all clocks have a finite amount of jitter and the clock period jitter should be included while specifying the clock uncertainty. One can specify different clock uncertainties for setup checks and for hold checks. The hold checks do not require the clock jitter to be included in the uncertainty and thus a smaller value of clock uncertainty is generally specified for hold. Q:设定clock uncertaity，为什么hold可以不考虑jitter产生的影响 Q:clock uncertainty如何影响setup和hold
clock latency
clock latency指时钟从时钟源到达end point的时间差值
set_clock_latency 2.0 [get_clocks USBCLK]
clock domain（时钟域）
一组由同一个时钟信号驱动的触发器，那么这组触发器就在同一个时钟域
如何判断两个或多个时钟域之间是彼此独立或彼此相关的？
A：两时钟域是否相关取决于是否有data path从一个clock domain到另一个clock domain，如果没有则可以判定为时钟域相互独立。
A question of interest is whether the clock domains are related or independent of each other. The answer depends on whether there are any data paths that start from one clock domain and end in the other clock domain. If there are no such paths, we can safely say that the two clock domains are independent of each other. This means that there is no timing path that starts from one clock domain and ends in the other clock domain.如果时钟域彼此相关，如何判断data path是真还是假？
A：
PVT operate conditions（PVT环境）
PVT可以分为typical，best，worst三种工艺环境
Item process voltage tempture TYP typical process nominal voltage nominal tempture BCF fast process highest voltage lowest tempture WCS slow process lowest voltage high to low TYP：typical
BCF：best case fast
WCS：worst case slow
WCS (Worst-Case Slow): Process is slow, temperature is highest(say 125C) and voltage is lowest (say nominal 1.2V minus 10%).For nanometer technologies that use low power supplies, there can be another worst-case slow corner that corresponds to the slow process, lowest power supply, and lowest temperature. The delays at low temperatures are not always smaller than the delays at higher temperatures.
在深纳米制程下，出现了温度反转现象，即在深纳米工艺下，温度越低，延迟越大
时序分析的同时还要考虑功耗，会加入另外两种工艺条件
ML(maximal leakage)极限功耗
TL(typical leakage)典型功耗
The environment conditions for power analysis are generally different than the ones used for static timing analysis. For power analysis, the operating conditions may be: i. ML (Maximal Leakage): Process is fast, temperature is highest (say 125C) and the voltage is also the highest (say 1.2V plus 10%). This corner corresponds to the maximum leakage power. For most designs, this corner also corresponds to the largest active power. ii. TL (Typical Leakage): Process is typical, temperature is highest(say 125C) and the voltage is nominal (say 1.2V). This refers to the condition where the leakage is representative for most designs since the chip temperature will be higher due to power dissipated in normal operation.STA基于加载的库做运算分析：
set_operating_conditions “WCCOM” -library mychip # Use the operating condition called WCCOM defined in the # cell library mychip.
Item process voltage tempture ML fast process highest voltage highest tempture TL typical process nominal voltage nominal tempture
冷知识：
nom_process：工艺缩放因子（cell按照缩放比例扩大缩小？），缩放因子越小时序分析时延结果越小，缩放因子越大，时延结果越大。
tree_type：定义互连线延时计算模型（best_case_tree worst_case_tree balance_tree）
标准库单元及模型
cell and library
哪些可以被称作是cell？
A cell could be a standard cell, an IO buffer, or a complex IP such as a USB core and so on.library中包含哪些信息？
In addition to timing information, the library cell description contains several attributes such as cell area and functionality, which are unrelated to timing but are relevant during the RTL synthesis process. library中包含除时序信息外还有cell的面积/功能这些与综合相关的信息。
pin capacitance（引脚容值）
每个cell都可以在其IO port上指定一个容值，但是多数情况下只对输入端口指定容值，所以在cell library中会看到输出引脚容值为0.
Every input and output of a cell can specify capacitance at the pin. In most cases, the capacitance is specified only for the cell inputs and not for the outputs, that is, the output pin capacitance in most cell libraries is 0. pin (INP1) { capacitance: 0.5; #most basic form rise_capacitance: 0.5; #rising transition pin capacitance rise_capacitance_range: (0.48, 0.52); #rising transition pin capacitance range fall_capacitance: 0.45; #falling transition pin capacitance fall_capacitance_range: (0.435, 0.46); #falling transition pin capacitance range . . . }
timing model
The cell timing models are intended to provide accurate timing for various instances of the cell in the design environment. The timing models are normally obtained from detailed circuit simulations of the cell to model the actual scenario of the cell operation. The timing models are specified for each timing arc of the cell. 单元时序模型旨在为设计环境中的各种单元实例提供准确的时序。通常从单元的详细电路仿真中获得时序模型，以对单元操作的实际情况进行建模。为cell的每个时序弧指定timing model。
The delay values have a direct correlation with the load capacitance - the larger the load capacitance, the larger the delay. In most cases, the delay increases with increasing input transition time. There are a few scenarios where the input threshold (used for measuring delay) is significantly different from the internal switching point of the cell. In such cases, the delay through the cell may show non-monotonic behavior with respect to the input transition time - a larger input transition time may produce a smaller delay especially if the output is lightly loaded. delay value和负载电容有直接的关系，负载电容值越大，delay也就越大（充放电时间长）。在大多数情况下，延迟随着输入转换时间的增加而增加。 在某些情况下，输入阈值（用于测量延迟）与单元的内部开关点明显不同。 在这种情况下，通过单元的延迟可能相对于输入转换时间表现出非单调行为-较大的输入转换时间可能会产生较小的延迟，尤其是在输出负载较轻的情况下。
linear delay model（线性延时模型）
线性时序模型中，cell delay和cell output transition time与input transition time和load capacitance呈现出线性关系。通常的表达形式为：
D = D0 + D1*s + D2*c D #delay s #input transition time c #output load capacitance D0/D1/D2 #constant value这种线性时序模型在工艺进入亚微米时代不再适用
non-linear delay model（非线性时序模型NLDM）
An NLDM model for delay is presented in a two-dimensional form, with the two independent variables being the input transition time and the output load capacitance, and the entries in the table denoting the delay. 非线性延时模型通过二维图表的方式进行建模，索引值分别为input timing transition和output load capacitance。通过图表找到对应的delay值。
通过分析最简单的cell反相器的查找表理解非线性模型
》图
inverter NLDM图表如上图所示：