Verilog练习:HDLBits笔记12

四、Sequential Logic 

Counters

1、Four-bit binary counter

Problem Statement:

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

Verilog练习:HDLBits笔记12

module top_module (
    input clk,
    input reset,      
    output [3:0] q
);
    always@(posedge clk)begin
        if(reset)
            q <= 4'd0;
        else if (q == 4'd15)
            q <= 4'd0;
        else 
            q <= q + 1'b1;
    end

endmodule

 2、Decade counter

Problem Statement:

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

Verilog练习:HDLBits笔记12

module top_module (
    input clk,
    input reset,        
    output [3:0] q
);
    always@(posedge clk)begin
        if(reset)
            q <= 4'd0;
        else if(q == 4'd9)
            q <= 4'd0;
        else 
            q <= q + 1'b1;
    end

endmodule

 3、Decade counter again

Problem Statement:

Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

Verilog练习:HDLBits笔记12

module top_module (
    input clk,
    input reset,
    output [3:0] q
);
    always@(posedge clk)begin
        if(reset)
            q <= 4'd1;
        else if(q == 4'd10)
            q <= 4'd1;
        else
            q <= q + 4'd1;
    end
            
endmodule

4、Slow decade counter 

Problem Statement:

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

Verilog练习:HDLBits笔记12

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q
);
    always@(posedge clk)begin
    	if(reset)
            q <= 4'd0;
        else if(slowena)begin
            if(q == 4'd9)
                q <= 4'd0;
            else 
                q <= q + 4'd1;
        end
    end


endmodule

5、Counter 1-12

Problem Statement:

Design a 1-12 counter with the following inputs and outputs:

  • Reset Synchronous active-high reset that forces the counter to 1
  • Enable Set high for the counter to run
  • Clk Positive edge-triggered clock input
  • Q[3:0] The output of the counter
  • c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.

You have the following components available:

  • the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
  • logic gates
module count4(
	input clk,
	input enable,
	input load,
	input [3:0] d,
	output reg [3:0] Q
);

The c_enablec_load, and c_d outputs are the signals that go to the internal counter's enableload, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); 
    assign c_enable = enable;
    
    assign c_load   = reset || ((Q == 4'd12) && (enable == 1'b1));
    
    assign c_d = c_load ? 4'd1 : 4'dx; 
    
    count4 instance1(.clk(clk), .enable(c_enable), .load(c_load), .d(c_d), .Q(Q));

endmodule

6、Counter 1000

Problem Statement:

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q
);
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);
    wire [3:0]Q0;
    wire [3:0]Q1;
    wire [3:0]Q2;
    
    bcdcount instance1(.clk(clk), .reset(reset), .enable(c_enable[0]), .Q(Q0));
    bcdcount instance2(.clk(clk), .reset(reset), .enable(c_enable[1]), .Q(Q1));
    bcdcount instance3(.clk(clk), .reset(reset), .enable(c_enable[2]), .Q(Q2));
    
    assign c_enable[0] = ~reset;
    assign c_enable[1] = ~reset && (Q0 == 4'd9);
    assign c_enable[2] = ~reset && (Q0 == 4'd9) && (Q1 == 4'd9);
    
    assign OneHertz = ((Q0 == 4'd9) && (Q1 == 4'd9) && (Q2 == 4'd9)) ? 1'b1 : 1'b0;
endmodule

 7、4-digit decimal counter

Problem Statement:

Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.

Verilog练习:HDLBits笔记12

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q
);
    
    reg[3:0]q0;
    reg[3:0]q1;
    reg[3:0]q2;
    reg[3:0]q3;
    
    always@(posedge clk)begin
        if(reset)
            q0 <= 4'd0;
        else if(q0 == 4'd9)
            q0 <= 4'd0;
        else 
            q0 <= q0 + 1'b1;
    end    
 
    assign ena[1] = (q0 == 4'd9) ? 1'b1 : 1'b0;
    
    always@(posedge clk)begin
        if(reset)
            q1 <= 4'd0;
        else if(q0 == 4'd9)
            if(q1 == 4'd9)
                q1 <= 4'd0;              
            else
                q1 <= q1 + 1'b1;            
        else 
            q1 <= q1;
    end    
    
    assign ena[2] = ((q0 == 4'd9)&&(q1 == 4'd9)) ? 1'b1 : 1'b0;
    
    always@(posedge clk)begin
        if(reset)
            q2 <= 4'd0;      
        else if((q0 == 4'd9)&&(q1 == 4'd9))
            if(q2 == 4'd9)
                q2 <= 4'd0;              
            else
                q2 <= q2 + 1'b1;      
        else
            q2 <= q2;
    end    
    
    assign ena[3] = ((q0 == 4'd9)&&(q1 == 4'd9)&&(q2 == 4'd9)) ? 1'b1 : 1'b0;
    
    always@(posedge clk)begin
        if(reset)
            q3 <= 4'd0; 
        else if((q0 == 4'd9)&&(q1 == 4'd9)&&(q2 == 4'd9))
            if(q3 == 4'd9)
                q3 <= 4'd0;              
            else
                q3 <= q3 + 1'b1;   
        else
            q3 <= q3;
    end  
        
    assign q = {q3,q2,q1,q0};

endmodule

 8、12-hour counter

Problem Statement:

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

Verilog练习:HDLBits笔记12

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss
);
    
    reg[3:0]ss1;
    reg[3:0]ss2;
    reg[3:0]mm1;
    reg[3:0]mm2;
    reg[3:0]hh1;
    reg[3:0]hh2;
       
    always@(posedge clk)begin
        if(reset)
            pm = 1'b0;
        else if((hh1 == 4'd1)&&(hh2 == 4'd1)&&(ss2 == 4'd5)&&(ss1 == 4'd9)&&(mm2 == 4'd5)&&(mm1 == 4'd9))
            pm <= ~pm;
    end
    
    always@(posedge clk)begin
        if(reset)
            ss1 <= 4'b0;
        else if(ena)begin
			if(ss1 == 4'd9)
            	ss1 <= 4'd0;
        	else 
           	 	ss1 <= ss1 + 1'b1;
        end
    end  
    
    always@(posedge clk)begin
        if(reset)
            ss2 <= 4'b0;
        else if(ena)begin
        	if((ss2 == 4'd5)&&(ss1 == 4'd9))
            	ss2 <= 4'd0;
        	else if(ss1 == 4'd9)
            	ss2 <= ss2 + 1'b1;
        end
    end  
    
     always@(posedge clk)begin
        if(reset)
            mm1 <= 4'b0;
         else if(ena)begin
        	if((mm1 == 4'd9)&&(ss2 == 4'd5)&&(ss1 == 4'd9))
            	mm1 <= 4'd0;
        	else if((ss2 == 4'd5)&&(ss1 == 4'd9))
            	mm1 <= mm1 + 1'b1;
         end
    end   
    
    always@(posedge clk)begin
        if(reset)
            mm2 <= 4'b0;
        else if(ena)begin
        	if((mm2 == 4'd5)&&(mm1 == 4'd9)&&(ss2 == 4'd5)&&(ss1 == 4'd9))
            	mm2 <= 4'd0;
        	else if((mm1 == 4'd9)&&(ss2 == 4'd5)&&(ss1 == 4'd9))
            	mm2 <= mm2 + 1'b1;
        end
    end    

     always@(posedge clk)begin
        if(reset)
            hh1 <= 4'd2;
         else if(ena)begin
        	if((ss2 == 4'd5)&&(ss1 == 4'd9)&&(mm2 == 4'd5)&&(mm1 == 4'd9))
            	if((hh1 == 4'd9)&&(hh2 == 4'd0))
                	hh1 <= 4'd0;
         		else if((hh1 == 4'd2)&&(hh2 == 4'd1))
                	hh1 <= 4'd1;
         		else
            		hh1 <= hh1 + 1'b1;
         end
    end
    
    always@(posedge clk)begin
        if(reset)
            hh2 <= 4'd1;
        else if(ena)begin
        	if((hh2 == 4'd1)&&(hh1 == 4'd2)&&(ss2 == 4'd5)&&(ss1 == 4'd9)&&(mm2 == 4'd5)&&(mm1 == 4'd9))
            	hh2 <= 4'd0;
        	else if((ss2 == 4'd5)&&(ss1 == 4'd9)&&(mm2 == 4'd5)&&(mm1 == 4'd9)&&(hh1 == 4'd9)) 
            	hh2 <= hh2 + 1'b1;
        end
    end  

    assign ss = {ss2,ss1};
    assign mm = {mm2,mm1};
    assign hh = {hh2,hh1};
    
endmodule
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