统计结果
C = A + B
输入位宽1 | 输入位宽2 | 输出位宽 | 逻辑深度 | cell count |
1024 | 1024 | 1024 | 32 | 11440 |
512 | 512 | 512 | 29 | 5444 |
256 | 256 | 256 | 27 | 2591 |
128 | 128 | 128 | 26 | 1217 |
64 | 64 | 64 | 21 | 600 |
32 | 32 | 32 | 24 | 265 |
16 | 16 | 16 | 19 | 22 |
8 | 8 | 8 | 10 | 9 |
4 | 4 | 4 | 5 | 12 |
备注
4bit + 4bit的dc映射,cell cout = 12
/
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP1
// Date : Wed Nov 17 10:39:36 2021
/
module test ( clk, rst_n, in_data1, in_data2, out_data );
input [3:0] in_data1;
input [3:0] in_data2;
output [3:0] out_data;
input clk, rst_n;
wire n1, n2, n3, n4, n5, n6, n9, n10;
OAI2BB1X1 U13 ( .A0N(in_data1[1]), .A1N(in_data2[1]), .B0(n6), .Y(n3) );
OAI211XL U14 ( .A0(in_data1[1]), .A1(in_data2[1]), .B0(in_data1[0]), .C0(
in_data2[0]), .Y(n6) );
XOR2X1 U15 ( .A(n9), .B(n10), .Y(out_data[1]) );
NAND2X2 U16 ( .A(in_data1[0]), .B(in_data2[0]), .Y(n9) );
XNOR2X1 U17 ( .A(in_data2[1]), .B(in_data1[1]), .Y(n10) );
XOR2X1 U18 ( .A(in_data2[0]), .B(in_data1[0]), .Y(out_data[0]) );
XOR2X1 U19 ( .A(n3), .B(n5), .Y(out_data[2]) );
XOR2X1 U20 ( .A(in_data2[2]), .B(in_data1[2]), .Y(n5) );
XOR2X1 U21 ( .A(n1), .B(n2), .Y(out_data[3]) );
XOR2X1 U22 ( .A(in_data2[3]), .B(in_data1[3]), .Y(n2) );
AOI2BB1X2 U23 ( .A0N(n3), .A1N(in_data1[2]), .B0(n4), .Y(n1) );
AOI21X1 U24 ( .A0(in_data1[2]), .A1(n3), .B0(in_data2[2]), .Y(n4) );
endmodule
8bit + 8bit的dc映射,cell cout = 9:
module test_DW01_add_0 ( A, B, SUM );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
wire n1;
wire [7:2] carry;
XOR3XL U1_7 ( .A(A[7]), .B(B[7]), .C(carry[7]), .Y(SUM[7]) );
ADDFX1 U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]), .S(SUM[6])
);
ADDFX1 U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]), .S(SUM[5])
);
ADDFX1 U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]), .S(SUM[4])
);
ADDFX1 U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]), .S(SUM[3])
);
ADDFX1 U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]), .S(SUM[2])
);
ADDFX1 U1_1 ( .A(A[1]), .B(B[1]), .CI(n1), .CO(carry[2]), .S(SUM[1]) );
AND2X2 U1 ( .A(B[0]), .B(A[0]), .Y(n1) );
XOR2X1 U2 ( .A(B[0]), .B(A[0]), .Y(SUM[0]) );
endmodule
module test ( clk, rst_n, in_data1, in_data2, out_data );
input [7:0] in_data1;
input [7:0] in_data2;
output [7:0] out_data;
input clk, rst_n;
test_DW01_add_0 add_13 ( .A(in_data1), .B(in_data2), .SUM(out_data) );
endmodule