题目：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 

    parameter LEFT = 0, RIGHT = 1, AAAH = 3;
    reg [1:0] state, next_state,state_before_fall;
   
    wire [2:0] sel;
    assign sel = {ground,bump_left,bump_right};
    always@(*) begin
        casex(sel)
            3'b0xx: next_state <= AAAH;
            3'b111: begin
                case(state)
                    LEFT: next_state <= RIGHT;
                    RIGHT: next_state <= LEFT;
                    AAAH: next_state <= state_before_fall;
                endcase
            end
            3'b110: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= RIGHT;
                endcase
            end
            3'b101: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= LEFT;
                endcase
            end
            3'b100:  begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= state;
                endcase
            end
        endcase
        /*if(!ground&&(state != AAAH))
            state_before_fall <= state;*/
        if(!ground&&(state == LEFT))
            state_before_fall <= LEFT;
        else if(!ground&&(state == RIGHT))
            state_before_fall <= RIGHT;
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == AAAH);
endmodule

但写成如下在网页运行则有问题，搬移到vivado没问题：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 

    parameter LEFT = 0, RIGHT = 1, AAAH = 3;
    reg [1:0] state, next_state,state_before_fall;
   
    wire [2:0] sel;
    assign sel = {ground,bump_left,bump_right};
    always@(*) begin
        casex(sel)
            3'b0xx: next_state <= AAAH;
            3'b111: begin
                case(state)
                    LEFT: next_state <= RIGHT;
                    RIGHT: next_state <= LEFT;
                    AAAH: next_state <= state_before_fall;
                endcase
            end
            3'b110: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= RIGHT;
                endcase
            end
            3'b101: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= LEFT;
                endcase
            end
            3'b100:  begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= state;
                endcase
            end
        endcase
        if(!ground&&(state != AAAH))
            state_before_fall <= state;
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == AAAH);
endmodule

vivado程序：（仅仅变了reg [1:0] state = LEFT）

module Lemmings2(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 

    parameter LEFT = 0, RIGHT = 1, AAAH = 3;
    reg [1:0] state = LEFT, next_state,state_before_fall;
   
    wire [2:0] sel;
    assign sel = {ground,bump_left,bump_right};
    always@(*) begin
        casex(sel)
            3'b0xx: next_state <= AAAH;
            3'b111: begin
                case(state)
                    LEFT: next_state <= RIGHT;
                    RIGHT: next_state <= LEFT;
                    AAAH: next_state <= state_before_fall;
                endcase
            end
            3'b110: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= RIGHT;
                endcase
            end
            3'b101: begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= LEFT;
                endcase
            end
            3'b100:  begin
                case(state)
                    AAAH: next_state <= state_before_fall;
                    default:next_state <= state;
                endcase
            end
        endcase
        if(!ground&&(state != AAAH))
            state_before_fall <= state;
    end
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= LEFT;
        else
            state <= next_state;
    end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == AAAH);
endmodule

tb文件

module tb_Lemmings2();

reg clk;
reg areset;
reg bump_left,bump_right,ground;

wire walk_left,walk_right,aaah;
Lemmings2 Lemmings2_1(
    .clk(clk),
    .areset(areset),    // Freshly brainwashed Lemmings walk left.
    .bump_left(bump_left),
    .bump_right(bump_right),
    .ground(ground),
    .walk_left(walk_left),
    .walk_right(walk_right),
    .aaah(aaah) ); 

initial begin
clk = 0;
areset = 0;
bump_left = 0;
bump_right = 0;
ground = 1;
#35;
ground = 0;
#30;
bump_left = 1;
ground = 1;
#20;
bump_left = 0;
ground = 0;
#30;
ground = 1;
#20;
$stop;
end

always #5 clk = !clk;
endmodule

两处运行结果对比：

有没有了解的人指导一下？