2011年的书，更像是论文集，不同章的作者不同，好多亚洲名字。
1 Introduction
Sunil P. Khatri and Kanupriya Gulati
1.1 Logic Decomposition
1.2 Boolean Satisfiability
1.3 Boolean Matching
1.4 Logic Optimization
Part I Logic Decomposition
2 Logic Synthesis by Signal-Driven Decomposition
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, and Tiziano Villa
2.3 P-Circuits
2.4 Multivariable Decomposition
3 Sequential Logic Synthesis Using Symbolic Bi-decomposition
Victor N. Kravets and Alan Mishchenko
3.2.1 "Less-Than-or-Equal" Relation
3.2.2 Parameterized Abstraction
3.3 Bi-decomposition of Incompletely Specified Functions
3.3.1 OR Decomposition
3.3.2 XOR Decomposition
3.4 Parameterized Decomposition
3.4.1 OR Parameterization
3.4.2 XOR Parameterization
3.5.1 Extraction of Incompletely Specified Logic
3.5.2 Exploring Decomposition Choices
3.5.3 Synthesis Algorithm
4 Boolean Factoring and Decomposition of Logic Networks
Robert Brayton, Alan Mishchenko, and Satrajit Chatterjee
4.3 General Non-disjoint Decompositions
4.4 Rewriting K-LUT networks
4.4.2 Cut Computation
4.4.3 Cuts with a DSD Structure
4.4.4 Cut Weight
4.4.5 Decomposition and Network Update
4.4.6 Finding the Maximum Support-Reducing Decomposition
4.4.7.1 Using Timing Information to Filter Candidate
4.4.7.2 Restricting Bound Sets for Balanced
4.4.7.3 Opportunistic MUX-Decomposition
4.5 Comparison with Boolean Matching
5 Ashenhurst Decomposition Using SAT and Interpolation
Hsuan-Po Lin, Jie-Hong Roland Jiang, and Ruei-Rung Lee
5.3.1 Functional Decomposition
5.3.2 Functional Dependency
5.3.3 Propositional Satisfiability and Interpolation
5.3.3.1 Refutation Proof and Craig Interpolation
5.3.3.2 Circuit-to-CNF Conversion
5.4.1 Single-Output Ashenhurst Decomposition
5.4.1.1 Decomposition with Known Variable Partition
5.4.1.2 Decomposition with Unknown Variable
Partition
5.4.2 Multiple-Output Ashenhurst Decomposition
5.4.3 Beyond Ashenhurst Decomposition
6 Bi-decomposition Using SAT and Interpolation
Ruei-Rung Lee, Jie-Hong Roland Jiang, and Wei-Lun Hung
6.3.1 Bi-Decomposition
6.3.2 Propositional Satisfiability
6.3.2.1 Refutation Proof and Craig Interpolation
6.3.3 Circuit to CNF Conversion
6.4.1 OR Bi-decomposition
6.4.1.1 Decomposition of Completely Specified Functions
6.4.1.2 Decomposition of Incompletely Specified Functions
6.4.2 AND Bi-decomposition
6.4.3 XOR Bi-decomposition
Part II Boolean Satisfiability
7 Boundary Points and Resolution
Eugene Goldberg and Panagiotis Manolios
7.3.1 Basic Propositions
7.3.2 Elimination of Boundary Points by Adding Resolvents
7.3.3 Boundary Points and Redundant Formulas
7.4 Resolution Proofs and Boundary Points
7.4.1 Resolution Proof as Boundary Point Elimination
7.4.2 SMR Metric and Proof Quality
7.5 Equivalence Checking Formulas
7.5.1 Building Equivalence Checking Formulas
7.5.2 Short Proofs for Equivalence Checking Formulas
7.8 Completeness of Resolution Restricted to Boundary Point Elimination
7.8.1 Cut Boundary Points
7.8.2 The Completeness Result
7.8.3 Boundary Points as Complexity Measure
7.9 Conclusions and Directions for Future Research
8 SAT Sweeping with Local Observability Don't-Cares
Qi Zhu, Nathan B. Kitchen, Andreas Kuehlmann, and Alberto Sangiovanni-Vincentelli
8.3.1 AND-INVERTER Graphs
8.3.2 SAT Sweeping
8.4 SAT Sweeping with Observability Don’t Cares
8.4.2 Observability Don't Cares
9 A Fast Approximation Algorithm for MIN-ONE SAT and Its Application on MAX-SAT Solving
Lei Fang and Michael S. Hsiao
9.3.1 RelaxSAT
9.3.2 Relaxation Heuristic Contents
9.5 Application Discussion: A RelaxSAT-Based MAX-SAT Solver
9.5.1 The New MAX-SAT Solver: RMAXSAT
9.5.2 Evaluation of MAX-SAT Solver
10 Algorithms for Maximum Satisfiability Using Unsatisfiable Cores
Joao Marques-Sila and Jordi Planes
10.2.1 The MaxSAT Problem
10.2.2 Solving MaxSAT with PBO
10.2.3 Relating MaxSAT with Unsatisfiable Cores
10.3 A New MaxSAT Algorithm
Part III Boolean Matching
11 Simulation and SAT-Based Boolean Matching for Large Boolean Networks
Kuo-Hua Wang, Chung-Ming Chan, and Jung-Chang Liu
11.2.1 Boolean Matching
11.2.2 Boolean Satisfiability
11.2.3 And-Inverter Graph
11.3 Detection of Functional Property Using S&S Approach
11.6 S&S-Based Boolean Matching Algorithm
11.6.2 Recursive-Matching Algorithm
11.6.3.1 Control of Random Vector Generation
11.6.3.2 Reduction of Simulation Time
11.6.3.3 Analysis of Space Complexity and Runtime
12 Logic Difference Optimization for Incremental Synthesis
Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, and Ruchir Puri
12.3 DeltaSyn
12.3.1 Phase I: Equivalence-Based Reduction
12.3.2 Phase II: Matching-Based Reduction
12.3.2.1 Subcircuit Enumeration
12.3.2.2 Subcircuit Matching
12.3.2.3 Subcircuit Covering
12.3.3 Phase III: Functional Hashing-Based Reduction
12.4 Empirical Validation
13 Large-Scale Boolean Matching
Hadi Katebi and Igor Markov
13.2.2 And-Inverter Graphs (AIGs)
13.2.3 Boolean Satisfiability and Equivalence Checking
13.3 Signature-Based Matching Techniques
13.3.1 Computing I/O Support Variables
13.3.2 Initial refinement of I/O clusters
13.3.3 Refining Outputs by Minterm Count
13.3.4 Refining I/O by Unateness
13.3.5 Scalable I/O Refinement by Dependency Analysis
13.3.6 Scalable I/O Refinement by Random Simulation
13.4 SAT-Based Search
13.4.1 SAT-Based Input Matching
13.4.2 Pruning Invalid Input Matches by SAT
13.4.3 SAT-Based Output Matching
13.4.4 Pruning Invalid Output Matches by SAT Counterexamples
13.4.5 Pruning Invalid I/O Matches Using Support Signatures
13.4.6 Pruning Invalid Input Matches Using Symmetries
13.4.7 A Heuristic for Matching Candidates
Part IV Logic Optimization
14 Algebraic Techniques to Enhance Common Sub-expression
Extraction for Polynomial System Synthesis
Sivaram Gopalakrishnan and Priyank Kalla
14.2.1 Kernel/Co-kernel Extraction
14.3.1 Polynomial Functions and Their Canonical Representations
14.3.2 Factorization
14.4.1 Common Coefficient Extraction
14.4.2 Common Cube Extraction
14.4.3 Algebraic Division
15 Automated Logic Restructuring with aSPFDs
Yu-Shen Yang, Subarna Sinha, Andreas Veneris, Robert Brayton, and Duncan Smith
15.2.1 Prior Work on Logic Restructuring
15.2.2 Sets of Pairs of Functions to Be Distinguished
15.3 Approximating SPFDs
15.3.1 Computing aSPFDs for Combinational Circuits
15.3.2 Computing aSPFDs for Sequential Circuits
15.3.3 Optimizing aSPFDs with Don’t Cares
15.3.3.1 Conflicts in Multiple Expected Traces
15.4 Logic Transformations with aSPFDs
15.4.1 SAT-Based Searching Algorithm
15.4.2 Greedy Searching Algorithm
15.5.1 Logic Restructuring of Combinational Designs
15.5.2 Logic Restructuring of Sequential Designs
16 Extracting Functions from Boolean Relations Using SAT and Interpolation
Jie-Hong Roland Jiang, Hsuan-Po Lin, and Wei-Lun Hung
16.3.1 Boolean Relation
16.3.2 Satisfiability and Interpolation
16.4.1 Single-Output Relation
16.4.1.1 Total Relation
16.4.1.2 Partial Relation
16.4.2 Multiple Output Relation
16.4.2.1 Determinization via Expansion Reduction
16.4.2.2 Determinization via Substitution Reduction
16.4.3 Deterministic Relation
16.4.4 Function Simplification
16.4.4.1 Support Minimization
16.4.4.2 Determinization Scheduling
17 A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations
Jeff L. Cobb, Kanupriya Gulati, and Sunil P. Khatri
17.4.1 BREL Boolean Relation Minimizer
17.5.1.1 Selecting Node Pairs
17.5.1.2 Building the Subnetwork
17.5.1.3 Computing the Boolean Relation RY
17.5.1.4 Quantification Scheduling
17.6.2 Parameter Selection
17.6.2.1 Selecting α
17.6.2.2 Selecting k1 and k2
17.6.2.3 Selecting thresh
17.6.4.3 Minimizing Single Nodes
17.6.4.4 Effects of Early Quantification
Part V Applications to Specialized Design Scenarios
18 Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms
Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja
18.3 Sets with Two Elements that Can Generate Arbitrary Decimal Probabilities
18.3.1 Generating Decimal Probabilities from the Input Probability Set S = {0.4, 0.5}
18.3.2 Generating Decimal Probabilities from the Input Probability Set S = {0.5, 0.8}
18.4 Sets with a Single Element that Can Generate Arbitrary Decimal Probabilities
19 Probabilistic Error Propagation in a Logic Circuit Using the Boolean Difference Calculus
Nasir Mohyuddin, Ehsan Pakbaznia, and Massoud Pedram
19.2 Error Propagation Using Boolean Difference Calculus
19.2.1 Partial Boolean Difference
19.2.2 Total Boolean Difference
19.2.3 Signal and Error Probabilities
19.3 Proposed Error Propagation Model
19.3.1 Gate Error Model
19.3.2 Error Propagation in 2-to-1 Mux Using BDEC
19.3.3 Circuit Error Model
19.4 Practical Considerations
19.4.1 Output Error Expression
19.4.2 Reconvergent Fanout
19.5 Simulation Results
19.6 Extensions to BDEC
19.6.1 Soft Error Rate (SER) Estimation Using BDEC
19.6.2 BDEC for Asymmetric Erroneous Transition Probabilities
19.6.3 BDEC Applied to Emerging Nanotechnologies
20 Digital Logic Using Non-DC Signals
Kalyana C. Bollapalli, Sunil P. Khatri, and Laszlo B. Kish
20.3.1 Standing Wave Oscillator
20.3.2 A Basic Gate
20.3.2.1 Multiplier
20.3.2.2 Low-Pass Filter
20.3.2.3 Output Stage
20.3.2.4 Complex Gates
20.3.3 Interconnects
20.4.1 Sinusoid Generator
20.4.2 Gate Optimization
20.4.3 Gate Operation
21 Improvements of Pausible Clocking Scheme for High-Throughput and High-Reliability GALS Systems Design
Xin Fan, Milos Krsti ˘ c, and Eckhard Grass ´
21.2 Analysis of Pausible Clocking Scheme
21.2.1 Local Clock Generators
21.2.2 Clock Acknowledge Latency
21.2.3 Throughput Reduction
21.2.3.1 Demand-Output (D-OUT) Port to Poll-Input (P-IN) Port Channel
21.2.3.2 Other Point-to-Point Channels
21.3.2.1 Double Latching Mechanism

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