Nexys4 DDR MIG控制器引脚文件

2022-05-17 13:52:29

目前网上只有ucf文件，vivado不兼容ucf格式

使用c++字符串转换的xdc格式代码

set_property -dict { PACKAGE_PIN R7   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN V6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN R8   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN U7   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN V7   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN R6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN U6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN R5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN T5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN U3   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN V5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN U4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN V4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN T4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN V1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN T3   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dq[] }];

set_property -dict { PACKAGE_PIN T6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dm[] }];

set_property -dict { PACKAGE_PIN U1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_dm[] }];

set_property -dict { PACKAGE_PIN U9   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_dqs_p[] }];

set_property -dict { PACKAGE_PIN V9   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_dqs_n[] }];

set_property -dict { PACKAGE_PIN U2   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_dqs_p[] }];

set_property -dict { PACKAGE_PIN V2   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_dqs_n[] }];

set_property -dict { PACKAGE_PIN N6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN K5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN R2   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN N5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN L4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN N1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN M2   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN P5   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN L3   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN T1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN M6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN P4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN M4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_addr[] }];

set_property -dict { PACKAGE_PIN R1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_ba[] }];

set_property -dict { PACKAGE_PIN P3   IOSTANDARD SSTL18_II  } [get_ports { ddr2_ba[] }];

set_property -dict { PACKAGE_PIN P2   IOSTANDARD SSTL18_II  } [get_ports { ddr2_ba[] }];

set_property -dict { PACKAGE_PIN L6   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_ck_p[] }];

set_property -dict { PACKAGE_PIN L5   IOSTANDARD DIFF_SSTL18_II  } [get_ports { ddr2_ck_n[] }];

set_property -dict { PACKAGE_PIN N4   IOSTANDARD SSTL18_II  } [get_ports { ddr2_ras_n }];

set_property -dict { PACKAGE_PIN L1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_cas_n }];

set_property -dict { PACKAGE_PIN N2   IOSTANDARD SSTL18_II  } [get_ports { ddr2_we_n }];

set_property -dict { PACKAGE_PIN M1   IOSTANDARD SSTL18_II  } [get_ports { ddr2_cke[] }];

set_property -dict { PACKAGE_PIN M3   IOSTANDARD SSTL18_II  } [get_ports { ddr2_odt[] }];

set_property -dict { PACKAGE_PIN K6   IOSTANDARD SSTL18_II  } [get_ports { ddr2_cs_n[] }];

使用C++写的转换代码（修改参数可以对任何代码使用）

#include <iostream>

#include <string>

using namespace std;

//set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }];

//NET "ddr2_addr[10]"                          LOC = "R2"      |   IOSTANDARD = SSTL18_II             ;         

string stringConver(string a) {

    string port;

    string pin;

    string type;

    int length = a.length();

    int i = ;

    for (; i < length; i++) {

        if (a[i] == '"') {

            port = a.substr(, i - );

            break;

        }

    }

    for (i++; i < length; i++) {

        if (a[i] == '"') {

            pin = a.substr(i+, );

            break;

        }

    }

    for (i++; i < length; i++) {

        if (a[i] == '=') {

            i++;

            for (int j =;; j++) {

                if (a[i + j] == ' ') {

                    type = a.substr(i+, j);

                    return (string)"set_property -dict { PACKAGE_PIN " + pin + "   IOSTANDARD " + type + " } [get_ports { " + port + " }];";

                }

            }

        }

    }

    return "";

}

int main() {

    string proto[];

    for (int i = ; i < ; i++) {

        getline(cin, proto[i]);

    }

    for (int i = ; i < ; i++) {

        cout << stringConver(proto[i]) << endl;

    }

    system("pause");

    return ;

}

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