HD，3G视频数据中行号的插入方法---Verilog代码实现
行号的生成：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2019/01/14 16:57:42
// Design Name:
// Module Name: line_num_pro
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module line_num_pro ( input wire clk,
input wire rst,
input wire eav,
input wire [:] vid_in, output wire [:] ln ); //----------------------------------------------------------------- assign v = vid_in[]; //----------------------------------------------------------------- reg last_v; always @(posedge clk or posedge rst)
begin
if(rst)
last_v <= 'b0;
else if(eav)
last_v <= v;
end //----------------------------------------------------------------- wire ln_load; assign ln_load = last_v & ~v; //----------------------------------------------------------------- assign ln_tc = ln_counter == ; //----------------------------------------------------------------- reg [:] ln_counter; always @(posedge clk or posedge rst)
begin
if(rst)
ln_counter <= 'd1; else if (eav)
begin
if(ln_load)
ln_counter <= 'd42;
else if(ln_tc)
ln_counter <= 'd1;
else
ln_counter <= ln_counter + 'b1;
end
end assign ln = ln_counter; //----------------------------------------------------------------- // ila_13 U576 (
// .clk(clk), // input wire clk // .probe0(vid_in), // input wire [9:0] probe0
// .probe1(eav), // input wire [0:0] probe1
// .probe2(v), // input wire [0:0] probe2
// .probe3(last_v), // input wire [0:0] probe3
// .probe4(ln_load), // input wire [0:0] probe4
// .probe5(ln_tc), // input wire [0:0] probe5
// .probe6(ln_counter), // input wire [10:0] probe6
// .probe7(ln) // input wire [10:0] probe7
// ); endmodule
行号的插入：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2019/01/15 17:06:40
// Design Name:
// Module Name: line_num_insert
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module line_num_insert( input wire insert_ln,
input wire ln_word0,
input wire ln_word1,
input wire [:] c_in,
input wire [:] y_in,
input wire [:] ln, output reg [:] c_out,
output reg [:] y_out ); //----------------------------------------------------------------------------- always @ (ln or insert_ln or c_in or ln_word0 or ln_word1)
if (insert_ln & ln_word0)
c_out <= {~ln[], ln[:], 'b00};
else if (insert_ln & ln_word1)
c_out <= {'b1000, ln[10:7], 2'b00};
else
c_out <= c_in; //--------------------------------------------------------------------------- always @ (ln or insert_ln or y_in or ln_word0 or ln_word1)
if (insert_ln & ln_word0)
y_out <= {~ln[], ln[:], 'b00};
else if (insert_ln & ln_word1)
y_out <= {'b1000, ln[10:7], 2'b00};
else
y_out <= y_in; //--------------------------------------------------------------------------- endmodule
生成ln_word0, ln_word1的脉冲指示信号：
reg ln_word0; always @(posedge hdmi_clk or posedge rst)
begin
if(rst)
ln_word0 <= 'b0; else if(eav)
ln_word0 <= 'b1; else
ln_word0 <= 'b0;
end //------------------------------------------------------------------------------------------------------------------------- reg ln_word1; always @(posedge hdmi_clk or posedge rst)
begin
if(rst)
ln_word1 <= 'b0; else if(ln_word0)
ln_word1 <= 'b1; else
ln_word1 <= 'b0;
end