Verilog HDL(HDLBits)
Verilog Language Basic
07-Vector-向量翻转
Given an 8-bit input vector [7:0], reverse its bit ordering.(将该向量翻转,第一位变最后一位,倒数第二变第二,以此类推)
module top_module(
input [7:0] in,
output [7:0] out
);
/*
integer i;
always@(*)
begin
for(i = 0; i <= 7; i = i + 1)
begin
out[i] = in[7-i];
end
end
*/
integer i;
always@(*)
begin
for(i = 0;i <= 7;i = i+1)
out[i] = in[7-i];
end
endmodule