Lecture 4 Page Table

• Isolation
• memory
• address spaces
• page tables(hardware support)
  • every app has its own map(page table)

• perpage(4KB, 4096 = 2^12 -> offset = 12)

  • virtual address(64) = {EXT(25) + index(27) + offset(12)}
  • RISC-V physical address(56) = {PNN(44, physical page number) + flag(12, inherited from virtual address)}

• RISC-V page tables

  

  • virtual address(64) = {EXT(25), L2(9), L1(9), L0(9), offset(12)}

    

    • L2、L1、L0: index into the every level page table
    • advantage: if large parts of the address space are not being used, you don’t have to have any page table entries for that

• Translation Look-aside Buffer(TLB)

  • cache of page table entries(PTE)
  • [VA, PA]

• page tables provide a level of indirection

• xv6 memory layout

  • virtual address space + physical address space(dram + io devices)
  • the mapping from virtual to physical is mostly in identity mapping

In the configuration of the physical hardware, there’s only so much space, and in the virtual memory layout, there’s also a max virtual address, by design is the virtual address made to be small enough?
Not necessarily, the virtual address space could be bigger than the physical memory, the physical memory could be bigger than virtual address space, it’s actually one of the cool parts about as we’ll see with the page tables, that’s extremely flexible.