本节书摘来自异步社区《现代体系结构上的UNIX系统：内核程序员的对称多处理和缓存技术（修订版）》一书中的第2章，第2.14节，作者：【美】Curt Schimmel著，更多章节内容可以访问云栖社区“异步社区”公众号查看
2.14 进一步的读物
[1] Agarwal, A., Hennessy, J., and Horowita, M., “Cache Performance of Operating System and Multiprogramming Workloads,” ACM Transactions on Computer System, Vol. 6, No. 4, November 1988, pp. 393-431.
[2] Agarwal, A., Horowitz, M., and Hennessy, J., “An Analytical Cache Model,” ACM Transactions on Computer System, Vol. 7, No. 2, May 1989.
[3] Alexander, C., Keshlear, W., Cooper, F., and Briggs, F., “Cache Memory Performance in a UNIX Environment,” SigArch News, Vol. 14, No. 3, June 1986, pp.41-70.
[4] Alexandridis, N., Design of Microprocessor Based Systems, Englewood Cliffs, NJ: Prentice Hall, 1993.
[5] Alpert, D., and Flynn, M., “Performance Tradeoffs for Microprocessor Cache Memories,” IEEE Micro, Vol. 8, No. 4, August 1988, pp. 44-55.
[6] Cohen, E.I., King, G.M., and Brady, J.T., “Storage Hierarchies,” IBM Systems Journal, Vol. 28, No. 1, 1989, pp. 62-76.
[7] Cole, C.B., “Advanced Cache Chips Make the 32-Bit Microprocessors Fly,” Electronics, Vol. 60, No. 13, June 11, 1988, pp. 78-9.
[8] Deville, Y., “A Low-Cost Usage-Based Replacement Algorithm for Cache Memories,” Computer Architecture News, Vol. 18, No. 4, December 1990, pp. 52-8.
[9] Duncombe, R.R., “The SPUR Instruction Unit: An On-Chip Instruction Cache Memory for a High Performance VLST Multiprocessor,” Technical Report UCB/CSD 87/307, Computer Science Division, University of California, Berkeley, August 1986.
[10] Easton, M., and Fagin, R., “Cold Start vs. Warm Start Miss Ratios,” Communications of the ACM, Vol. 21, No. 10, October 1978, pp. 866-72.
[11] Gecsei, J. “Determining Hit Ratios for Multilevel Hierarchies,” IBM Journal of Research and Development, Vol. 18, No. 4, July 1974, pp. 316-27.
[12] Goodman, J.R., “Using Cache Memory to Reduce Processor-Memory Traffic,” Proceedings of the 10th Annual Symposium on Computer Architecture, June 1983. pp. 124-31.
[13] Haikala, I.J., and Kutvonen, P.H., “Split Cache Organizations,” Performance '84, 1984, pp. 459-72.
[14] Handy, J., The Cache Memory Book, Boston, MA: Academic Press, 1993.
[15] Higbie, L., “Quick and Easy Cache Performance Analysis,” Computer Architecture News, Vol. 18, No. 2, June 1990, pp. 33-44.
[16] Hill, M.D., “The Case for Direct-Mapped Caches,” IEEE Computer, Vol. 21, No. 12, December 1988, pp. 25-41.
[17] Hill, M.D., and Smith, A.J., “Experimental Evaluation of On-Chip Microprocessor Cache Memories,” Proceedings of the 11th Annual International Symposium on Computers Architecture, June 1984, pp. 158-66.
[18] Hill, M.D., and smith, A.J., “Evaluating Associativity in CPU Caches,” IEEE Transactions on Computers, Vol. 38, No. 12, December 1989, pp. 1612-30.
[19] Jouppi, N.P., “Cache Write Policies and Performance,” Proceedings of the 20th Annual International Symposium on Computer Architecture, May 1993, pp. 191-201.
[20] Laha, S., Patel, J.H., and Iyer, R.K., “Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems,” IEEE Transactions on Computers, Vol. 37, No. 11, November 1988, pp.1325-36.
[21] Lorin, H., Introduction to Computer Architecture and Organization, Second Edition, New York, NY: John Wiley & Sons, 1989.
[22] Mano, M.M., Computer System Architecture, Third Edition, Englewood Cliffs, NJ: Prentice Hall, 1993.
[23] Przybylski, S.A., Cache and Memory Hierarchy Design: A Performance-Directed Approach, San Mateo, CA: Morgan Kaufmann Publishers, 1990.
[24] Rao, G.S., “Performance Analysis of Cache Memories,” Journal of the ACM, Vol. 25, No. 3, July 1978, pp. 378-95.
[25] Short, R.T., and Levy, H.M., “A Simulation Study of Two-Level Caches,” Proceedings of the 15th Annual International Symposium on Computer Architecture, June 1988, pp. 81-9.
[26] Smith, A.J., “A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Main Memory,” IEEE Transactions on Software Engineering, Vol. 4, No. 2, March 1978, pp. 121-30.
[27] Smith, A.J., “Sequential Program Prefetching in Memory Hierarchies,” IEEE Computer, Vol. 11, No. 12, December 1978, PP. 7-21.
[28] Smith, A.J., “Cache Memories,” ACM Computing Surveys, Vol. 14, No. 3, September 1982, pp.473-530.
[29] Smith, A.J., “Cache Evaluation and the Impact of Workload Choice,” Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985, pp. 64-73.
[30] Smith, A.J., “Problems, Directions, and Issues in Memory Hierarchies,” Proceedings of the 18th Annual Hawaii Conference on System Sciences, 1985, pp. 468-76.
[31] Smith, A.J., “Bibliography and Readings on CPU Cache Memories and Related Topics,” Computer Architecture News, Vol. 14, No. 1, January 1986, pp. 22-42.
[32] Smith, A.J., “Design of CPU Cache Memories,” Proceedings of the IEEE TENCON, August 1987, pp. 30.2.1-30.2.10.
[33] Smith, A.J., “Line (Block) Size Choice for CPU Cache Memories,” IEEE Transactions on Computers, Vol. 36, No. 9, September 1987, pp. 1063-75.
[34] Stone, H.S., High Performance Computer Architecture, Third Edition, Reading, MA: Addison-Wesley, 1993.
[35] Strecker, W.D., “Transient Behavior of Cache Memories,” ACM Transactions on Computer Systems, Vol. 1, No. 4, November 1983, pp. 281-93.
[36] Smith, J.E., and Goodman, J.R., “A Study of Instruction Cache Organizations and Replacement Policies,” Proceedings of the 10th Annual International Symposium on Computer Architecture, June 1983, pp. 64-73.
[37] Thiebaut, D.F., “On the Fractal Dimension of Computer Programs and Its Application to the Prediction of the Cache Miss Ratio,” IEEE Transactions on Computers, Vol. 38, No. 7, July 1989, pp. 1012-27.
[38] Thompson, J.G., “Efficient Analysis of Caching Systems,” Technical Report UCB/CSD 87/374, Computer Science Division, University of California, Berkeley, October 1987.
[39] Thompson, J.G., and Smith, A.J., “Efficient (Stack) Algorithms for Analysis of Write-Back and Sector Memories,” ACM Transactions on Computer Systems, Vol. 7, No.1, February 1989, pp. 78-116.
[40] Welch, T.A., “Memory Hierarchy Configuration Analysis,” IEEE Transactions on Computers, Vol. C-27, No.5, May 1978, pp. 408-13.