文章目录
前言
UVM（Universal Verification Methodology），其正式版是在2011年2月由Accellera推出的，得到了Sysnopsys、Mentor和Cadence的支持。UVM几乎完全继承了OVM，同时又采纳了Synopsys在VMM中的寄存器解决方案RAL。同时，UVM还吸收了VMM中的一些优秀的实现方式。可以说，UVM继承了VMM和OVM的优点，克服了各自的缺点，代表了验证方法学的发展方向。
本文以《UVM实战》实战中源代码为例，介绍了UVM验证平台的搭建过程，了解各个组件的构成及UVM整体框架。
DUT介绍
DUT的功能为： 通过rxd接收数据，再通过txd发送出去。其中rx_dv是接收的数据有效指示，tx_en是发送的数据有效指示。
代码如下：
module dut(clk,rst_n,rxd,rx_dv,txd,tx_en);
input clk;
input rst_n;
input [7:0]rxd;
input rx_dv;
output [7:0]txd;
output tx_en;
reg[7:0] txd;
reg tx_en;
always @(posedge clk) begin
if (!rst_n) begin
txd <= 8'b0;
tx_en <= 1'b0;
end
else begin
txd <= rxd;
tx_en <= rx_dv;
end
end
endmodule
dirver模块
`ifndef MY_DRIVER_SV
`define MY_DRIVER_SV
`include "my_transaction.sv"
class my_driver extends uvm_driver#(my_transaction);
virtual my_if vif;
`uvm_component_utils(my_driver)//factory Registration mechanism
function new(string name = "my_driver", uvm_component parent = null);
super.new(name, parent);
`uvm_info("my_driver", "new is called", UVM_LOW);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("my_driver", "build_phase is called", UVM_LOW);
if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
`uvm_fatal("my_driver", "virtual interface must be set for vif!!!")
endfunction
extern task main_phase (uvm_phase phase);
extern task drive_one_pkt(my_transaction tr);
endclass
task my_driver::main_phase(uvm_phase phase);
vif.data <= 8'b0;
vif.valid <=1'b0;
while(!vif.rst_n ) begin
@(posedge vif.clk);
end
while(1) begin
seq_item_port.try_next_item(req);
drive_one_pkt(req);
seq_item_port.item_done();//When the driver completes, call item_done to notify sequencer: Handshake mechanism
end
endtask
task my_driver::drive_one_pkt(my_transaction tr);
byte unsigned data_q[];
int data_size;
data_size = tr.pack_bytes(data_q)/8;
`uvm_info("my_driver", "begin to drive one pkt", UVM_LOW);
repeat(3) @(posedge vif.clk);
for(int i = 0; i<data_size; i++) begin
@(posedge vif.clk);
vif.valid <= 1'b1;
data_q = new(data_size);
vif.data <= data_q[i];
end
@(posedge vif.clk);
vif.valid <= 1'b0;
`uvm_info("my_driver", "end drive one pkt", UVM_LOW);
endtask
`endif
在UVM验证平台中，driver只负责驱动transaction，而不负责产生transaction。激励的产生是通过sequence机制作用。其有两大组成部分，一是sequence，二是sequencer。driver作为uvm_component组件，需要通过UVM的工厂机制在uvm_component_utils(my_driver)中完成注册。代码中的build_phase是UVM中内建的一个phase。当UVM启动后，会自动执行
build_phase。build_phase在new函数之后main_phase之前执行。在build_phase中主要通过config_db的set和get操作来传递一些数据，以及实例化成员变量等。需要注意的是，这里需要加入super.build_phase语句，因为在其父类的build_phase中执行了一些必要的操作，这里必须显式地调用并执行它。build_phase与main_phase不同的一点在于，build_phase是一个函数phase，而main_phase是一个任务phase，build_phase是不消耗仿真时间的。build_phase总是在仿真时间（$time函数打印出的时间）为0时执行。
在此driver中，通过drive_one_pkt函数将激励驱动到vif.data上，pack_bytes为打包函数，可以将tr中数据打包成byte流。
uvm_sequence与uvm_sequencer
sequence不属于验证平台的任何一部分，但是它与sequencer之间有密切的联系，这点从二者的名字就可以看出来。只有sequencer的帮助下，sequence产生出的transaction才能最终送给driver；同样，sequencer只有在sequence出现的情况下才能体现其价值，如果没有sequence，sequencer就几乎没有任何作用。sequence就像是一个弹夹，里面的子弹是transaction，而sequencer是一把枪。弹夹只有放入枪中才有意义，枪只有在放入弹夹后才能发挥威力。
如上图所示，可以看出，sequence不属于验证平台，只是将数据发送给sequencer，然后使sequencer与driver握手，完成数据的一次传输过程。
`ifndef MY_SEQUENCE__SV
`define MY_SEQUENCE__SV
`include "my_transaction.sv"
class my_sequence extends uvm_sequence #(my_transaction);
my_transaction m_trans;
function new(string name= "my_sequence");
super.new(name);
endfunction
virtual task body();
if(starting_phase != null)
starting_phase.raise_objection(this);
repeat (10) begin
`uvm_do(m_trans)//macro of `uvm_do create a my_transaction instance m_trans;randomize it;Finally give it away sequencer.
end
#1000;
if(starting_phase != null)
starting_phase.drop_objection(this);//相当于$finish
endtask
`uvm_object_utils(my_sequence)
endclass
`endif
如上所示为sequence的代码，在uvm_sequence这个基类中，有一个变量名为starting_phase，可以通过它进行提起和撤销objection。
my_transaction模块
transaction是一个抽象的概念。一般来说，物理协议中的数据交换都是以帧或者包为单位的，通常在一帧或者一个包中要定义
好各项参数，每个包的大小不一样。很少会有协议是以bit或者byte为单位来进行数据交换的。以以太网为例，每个包的大小至少
是64byte。这个包中要包括源地址、目的地址、包的类型、整个包的CRC校验数据等。transaction就是用于模拟这种实际情况，一笔transaction就是一个包。在不同的验证平台中，会有不同的transaction。
`ifndef MY_TRANSACTION_SV
`define MY_TRANSACTION_SV
`include "uvm_macros.svh"//a file in the UVM
import uvm_pkg::*;
class my_transaction extends uvm_sequence_item;
rand bit[47:0] dmac;//A 48-bit Ethernet destination address
rand bit[47:0] smac;// a 48-bit Ethernet source address
rand bit[15:0] ether_type;
rand byte pload[];//the size of the data
rand bit[31:0] crc;
constraint pload_cons{pload.size >= 46; pload.size <= 1500;}
function bit [31:0] calc_crc;
return 32'h0;
endfunction
function void post_randomize();
crc = calc_crc;
endfunction
`uvm_object_utils_begin(my_transaction)
`uvm_field_int(dmac, UVM_ALL_ON)
`uvm_field_int(smac, UVM_ALL_ON)
`uvm_field_int(ether_type, UVM_ALL_ON)
`uvm_field_array_int(pload, UVM_ALL_ON)
`uvm_field_int(crc, UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "my_transaction");
super.new(name);
endfunction
endclass
`endif
注意：1. transaction的基类是uvm_sequence_item。在UVM中，所有的transaction都要从uvm_sequence_item派生，只有从uvm_sequence_item派生的transaction才可以使用UVM中强大的sequence机制。2. 可以通过域的自动化实现my_transaction的factory注册，从而可以直接调用copy、compare、print等函数，而无需自己定义。
加入monitor
验证平台必须监测DUT的行为，只有知道DUT的输入输出信号变化之后，才能根据这些信号变化来判定DUT的行为是否正
确。验证平台中实现监测DUT行为的组件是monitor。driver负责把transaction级别的数据转变成DUT的端口级别，并驱动给DUT，monitor的行为与其相对，用于收集DUT的端口数据，并将其转换成transaction交给后续的组件如reference model、scoreboard等处理。
`ifndef MY_MONITOR__SV
`define MY_MONITOR__SV
`include "my_transaction.sv"
class my_monitor extends uvm_monitor;
virtual my_if vif;
uvm_analysis_port #(my_transaction) ap;//Parameterized class
`uvm_component_utils(my_monitor)
function new(string name = "my_monitor", uvm_component parent = null);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
`uvm_fatal("my_monitor", "virtual interface must be set for vif!!!")
ap = new("ap", this);
endfunction
extern task main_phase(uvm_phase phase);
extern task collect_one_pkt(my_transaction tr);
endclass
task my_monitor::main_phase(uvm_phase phase);
my_transaction tr;
while(1) begin
tr = new("tr");
collect_one_pkt(tr);
ap.write(tr);
end
endtask
task my_monitor::collect_one_pkt(my_transaction tr);
byte unsigned data_q[$];
byte unsigned data_array[];
logic [7:0] data;
logic valid = 0;
int data_size;
while(1) begin//因为monitor需要时刻收集数据
@(posedge vif.clk);
if(vif.valid) break;
end
`uvm_info("my_monitor", "begin to collect one pkt", UVM_LOW);
while(vif.valid) begin
data_q.push_back(vif.data);
@(posedge vif.clk);
end
data_size = data_q.size();
data_array = new[data_size];//动态数组使用前必须new
for(int i =0; i<data_size; i++) begin
data_array[i] = data_q[i];
end
tr.pload = new[data_size - 18];//pload in tr is a dynamic array, need to call pload in tr,Unpack_bytes specifies the size previously
data_size = tr.unpack_bytes(data_array)/8;
`uvm_info("my_monitor", "end collect one pkt, print it:", UVM_LOW);
endtask
`endif
collect_one_pkt与driver中的driver_one_pkt功能相似，收集被driver驱动到总线上的数据，通过unpack_bytes函数将data_array中的bytes流数据解析成tr数据。
加入agent
driver和monitor处理的是同一种协议，在同样一套既定的规则下做着不同的事情。由于二者的这种相似性，UVM中通常将二者封装在一起，成为一个agent。因此，不同的agent就代表了不同的协议，由于sequencer与driver的关系非常密切，因此要把其加入agent中。
`ifndef MY_AGENT__SV
`define MY_AGENT__SV
`include "my_driver.sv"
`include "my_monitor.sv"
`include "my_sequencer.sv"
class my_agent extends uvm_agent;
my_sequencer sqr;
my_driver drv;
my_monitor mon;
uvm_analysis_port #(my_transaction) ap;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
`uvm_component_utils(my_agent)
endclass
function void my_agent::build_phase(uvm_phase phase);
super.build_phase(phase);
if(is_active == UVM_ACTIVE) begin//The default value of is_active is UVM_ACTIVE
sqr = my_sequencer::type_id::create("sqr", this);
drv = my_driver::type_id::create("drv", this);
end
mon = my_monitor::type_id::create("mon", this);
endfunction
function void my_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (is_active == UVM_ACTIVE) begin
drv.seq_item_port.connect(sqr.seq_item_export);//connect uvm_driver and uvm_sequencer
end
ap = mon.ap;
endfunction
`endif
在connect_phase中，将driver中的seq_item_port和在uvm_sequencer中有成员变量seq_item_export，这两者之间可以建立一个“通道”。含义：driver向sequencer申请数据，然后等待sequence将数据发送给sequencer并将数据给driver，且会复制一份数据， 当数据传输完成时，driver会发送seq_item_port.item_done信号给sequencer，未没有收到此信号之前，会一直保留数据。
加入reference model
reference model用于完成和DUT相同的功能。reference model的输出被scoreboard接收，用于和DUT的输出相比较。DUT如果很复杂，那么reference model也会相当复杂。
`ifndef MY_MODEL__SV
`define MY_MODEL__SV
`include "my_transaction.sv"
class my_model extends uvm_component;
uvm_blocking_get_port #(my_transaction) port;
uvm_analysis_port #(my_transaction) ap;//send to scoreboard
extern function new(string name, uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);
`uvm_component_utils(my_model)
endclass
function my_model::new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void my_model::build_phase(uvm_phase phase);
super.build_phase(phase);
port = new("port", this);
ap = new("ap", this);
endfunction
task my_model::main_phase(uvm_phase phase);
my_transaction tr;
my_transaction new_tr;
super.main_phase(phase);
while(1) begin
port.get(tr);
new_tr = new("new_tr");
new_tr.copy(tr);
`uvm_info("my_model", "get one transaction, copy and print it:", UVM_LOW)
new_tr.print();
ap.write(new_tr);//write function of uvm_analysis_port
end
endtask
`endif
加入scoreboard
my_scoreboard要比较的数据一是来源于reference model，二是来源于o_agt的monitor。前者通过exp_port获取，而后者通过
act_port获取。在main_phase中通过fork建立起了两个进程，一个进程处理exp_port的数据，当收到数据后，把数据放入
expect_queue中；另外一个进程处理act_port的数据，这是DUT的输出数据，当收集到这些数据后，从expect_queue中弹出之前从exp_port收到的数据，并调用my_transaction的my_compare函数。采用这种比较处理方式的前提是exp_port要比act_port先收到数据。由于DUT处理数据需要延时，而reference model是基于高级语言的处理，一般不需要延时，因此可以保证exp_port的数据在act_port的数据之前到来。
`ifndef MY_SCOREBOARD__SV
`define MY_SCOREBOARD__SV
`include "my_transaction.sv"
class my_scoreboard extends uvm_scoreboard;
my_transaction expect_queue[$];
uvm_blocking_get_port #(my_transaction) exp_port;//from my_model
uvm_blocking_get_port #(my_transaction) act_port;//from o_agent
`uvm_component_utils(my_scoreboard)
extern function new(string name, uvm_component parent = null);
extern virtual function void build_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);
endclass
function my_scoreboard::new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction
function void my_scoreboard::build_phase(uvm_phase phase);
super.build_phase(phase);
exp_port = new("exp_port", this);
act_port = new("act_port", this);
endfunction
task my_scoreboard::main_phase(uvm_phase phase);
my_transaction get_expect, get_actual, tmp_tran;
bit result;
super.main_phase(phase);
fork
while (1) begin
exp_port.get(get_expect);
expect_queue.push_back(get_expect);
end
while (1) begin
act_port.get(get_actual);
if(expect_queue.size() > 0) begin
tmp_tran = expect_queue.pop_front();
result = get_actual.compare(tmp_tran);
if(result) begin
`uvm_info("my_scoreboard", "Compare SUCCESSFULLY", UVM_LOW);
end
else begin
`uvm_error("my_scoreboard", "Compare FAILED");
$display("the expect pkt is");
tmp_tran.print();
$display("the actual pkt is");
get_actual.print();
end
end
else begin
`uvm_error("my_scoreboard", "Received from DUT, while Expect Queue is empty");
$display("the unexpected pkt is");
get_actual.print();
end
end
join
endtask
`endif
加入env
`ifndef MY_ENV_SV
`define MY_ENV_SV
`include "my_agent.sv"
`include "my_model.sv"
`include "my_scoreboard.sv"
class my_env extends uvm_env;
my_agent i_agt;
my_agent o_agt;
my_model mdl;
my_scoreboard scd;
uvm_tlm_analysis_fifo #(my_transaction) agt_mdl_fifo;
uvm_tlm_analysis_fifo #(my_transaction) agt_scb_fifo;
uvm_tlm_analysis_fifo #(my_transaction) mdl_scb_fifo;
function new(string name = "my_env", uvm_component parent);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
i_agt = my_agent::type_id::create("i_agt", this);
o_agt = my_agent::type_id::create("o_agt", this);
i_agt.is_active = UVM_ACTIVE;
o_agt.is_active = UVM_PASSIVE;//No driver is required on the output port, just need to monitor the signal
mdl = my_model::type_id::create("mdl", this);
scd = my_scoreboard::type_id::create("scd", this);
agt_mdl_fifo = new("agt_mdl_fifo", this);
agt_scb_fifo = new("agt_scb_fifo", this);
mdl_scb_fifo = new("mdl_scb_fifo", this);
endfunction
extern virtual function void connect_phase(uvm_phase phase);
`uvm_component_utils(my_env)
endclass
function void my_env::connect_phase(uvm_phase phase);
super.connect_phase(phase);
i_agt.ap.connect(agt_mdl_fifo.analysis_export);//the connect_phase of my_agent performed before the my_env
mdl.port.connect(agt_mdl_fifo.blocking_get_export);
mdl.ap.connect(mdl_scb_fifo.analysis_export);
scd.exp_port.connect(mdl_scb_fifo.blocking_get_export);
o_agt.ap.connect(agt_scb_fifo.analysis_export);
scd.act_port.connect(agt_scb_fifo.blocking_get_export);
endfunction
`endif
这个容器类env中实例化了driver、monitor、reference model和scoreboard等。在调用run_test时，传递的参数不再是my_driver，而是这个容器类，即让UVM自动创建这个容器类的实例。在UVM中，这个容器类称为uvm_env
验证平台顶层top_tb
`timescale 1ns/1ps
`include "uvm_macros.svh"//a file in the UVM
import uvm_pkg::*;//uvm library
`include "my_transaction.sv"
`include "my_sequencer.sv"
`include "my_driver.sv"
`include "my_monitor.sv"
`include "my_agent.sv"
`include "my_model.sv"
`include "my_scoreboard.sv"
`include "my_env.sv"
`include "base_test.sv"
`include "my_case0.sv"
interface my_if(input clk, input rst_n);
logic [7:0] data;
logic valid;
endinterface
module top_tb;
reg clk;
reg rst_n;
reg [7:0]rxd;
reg rx_dv;
wire [7:0]txd;
wire tx_en;
my_if input_if(clk, rst_n);
my_if output_if(clk, rst_n);
dut my_dut(.clk(clk),
.rst_n(rst_n),
.rxd(input_if.data),
.rx_dv(input_if.valid),
.txd(output_if.data),
.tx_en(output_if.valid));
initial begin//clock generation
clk = 0;
forever begin
#100 clk <= ~clk;
end
end
initial begin
rst_n = 1'b0;
#2 $display ("rst_n is %0b", rst_n);
#1000;
rst_n = 1'b1;
end
//Passed to my_drive through config_db
initial begin
run_test("my_case0");//Automatic instance creation by +UVM_TEST_NAME
end
initial begin
uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);//The fourth parameter indicates which interface to add
uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);
uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);
end
endmodule
在top_tb中通过set设置virtual interface，而在driver或者monitor中通过get函数得到virtual interface。
在run_test中可以启动测试用例，可以通过 +UVM_TEST_NAME命令指定case启动。
创建base_test
base_test派生自uvm_test，使用uvm_component_utils宏来注册到factory中。在build_phase中实例化my_env，并设置sequencer的default_sequence来启动sequencer。除了实例化env外，base_test中做的事情在不同的公司各不相同。上面的代码中出现了report_phase，在report_phase中根据UVM_ERROR的数量来打印不同的信息。一些日志分析工具可以根据打印的信息来判断DUT是否通过了某个测试用例的检查。
`ifndef BASE_TEST__SV
`define BASE_TEST__SV
`include "my_sequence.sv"
`include "my_env.sv"
`include "my_sequencer.sv"
class base_test extends uvm_test;
my_env env;//all case need to instantiated env
function new(string name = "base_test", uvm_component parent = null);
super.new(name,parent);
endfunction
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void report_phase(uvm_phase phase);
`uvm_component_utils(base_test)
endclass
function void base_test::build_phase(uvm_phase phase);
super.build_phase(phase);
env = my_env::type_id::create("env", this);
uvm_config_db#(uvm_object_wrapper)::set(this,
"env.i_agt.sqr.main_phase",
"default_sequence",
my_sequence::type_id::get());start the sequence by default_sequence
endfunction
function void base_test::report_phase(uvm_phase phase);
uvm_report_server server;
int err_num;
super.report_phase(phase);
server = get_report_server();
err_num = server.get_severity_count(UVM_ERROR);
if (err_num != 0) begin
$display("TEST CASE FAILED");
end
else begin
$display("TEST CASE PASSED");
end
endfunction
`endif
测试用例case添加
测试用例都是基于base_test派生的一个类
`ifndef MY_CASE0__SV
`define MY_CASE0__SV
`include "base_test.sv"
class case0_sequence extends uvm_sequence #(my_transaction);
my_transaction m_trans;
function new(string name= "case0_sequence");
super.new(name);
endfunction
virtual task body();
if(starting_phase != null)
starting_phase.raise_objection(this);
repeat (10) begin
`uvm_do(m_trans)
end
#100;
if(starting_phase != null)
starting_phase.drop_objection(this);
endtask
`uvm_object_utils(case0_sequence)
endclass
class my_case0 extends base_test;
function new(string name = "my_case0", uvm_component parent = null);
super.new(name,parent);
endfunction
extern virtual function void build_phase(uvm_phase phase);
`uvm_component_utils(my_case0)
endclass
function void my_case0::build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(uvm_object_wrapper)::set(this,
"env.i_agt.sqr.main_phase",
"default_sequence",
case0_sequence::type_id::get());//start directly by case0_sequence.start
endfunction
`endif