FPGA交通灯控制器verilog-QuratusⅡ
一、设计并调试好一个由南北方向和东西方向汇合点形成的十字交叉路口的交通灯控制器，具体要求如下：
（1）掌握quaruts 软件的使用方法
（2）熟悉GW48实验开发系统的基本使用方法
（3）掌握verilog综合系统的设计方法
（4）了解交通灯的控制原理
(1) 南北、东西方向各设有一个左转、黄、绿、红指示灯，两个显示数码管。
(2) 突发事件下，两个方向都亮红灯
(3) 正常情况下，交替通行，绿灯亮的时间为40s，左转灯亮为15s，黄灯过度时间为5s，在每个方向上倒计时显示时间。
二、代码
module test10(clk, tufa,clkout,rst_n,led);
input clk;
input rst_n;
input tufa;
output [7:0] led;
output clkout;
reg [7:0] led;
reg [4:0] time_left;
reg [4:0] state;
reg clkout;
reg [31:0] cnt;
parameter [8:0] S0 = 4'b0000,
S1 = 4'b0001,
S2 = 4'b0010,
S3 = 4'b0011,
S4 = 4'b0100,
S5 = 4'b0101,
S6 = 4'b0110,
S7 = 4'b0111,
S8 = 4'b1000;
always @(posedge clk)
begin //板子时钟为100MHZ，
if(cnt == 32'd9999_9999)
begin
clkout <= 1'b1;
cnt <= 32'd0;
end
else
begin
clkout <= 1'b0;
cnt <= cnt + 32'd1;
end
end
always @(posedge clk)
if(!tufa)
begin
if(!rst_n)
begin
state <= S1;
time_left <= 5'd14;
led <= 8'b1000_0001;
end
else
begin
case(state)
S1:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S2;
time_left <= 5'd4;
led <= 8'b0100_0001;
end
else
begin
state <= S1;
time_left <= time_left-1'b1;
led <= 8'b1000_0001;
end
end
end
S2:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S3;
time_left <= 5'd39;
led <= 8'b0010_0001;
end
else
begin
state <= S2;
time_left <= time_left-1'b1;
led <= 8'b0100_0001;
end
end
end
S3:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S4;
time_left <= 5'd4;
led <= 8'b0100_0001;
end
else
begin
state <= S3;
time_left <= time_left-1'b1;
led <= 8'b0010_0001;
end
end
end
S4:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S5;
time_left <= 5'd14;
led <= 8'b0001_1000;
end
else
begin
state <= S4;
time_left <= time_left-1'b1;
led <= 8'b0100_0001;
end
end
end
S5:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S6;
time_left <= 5'd4;
led <= 8'b0001_0100;
end
else
begin
state <= S5;
time_left <= time_left-1'b1;
led <= 8'b0001_1000;
end
end
end
S6:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S7;
time_left <= 5'd39;
led <= 8'b0001_0010;
end
else
begin
state <= S6;
time_left <= time_left-1'b1;
led <= 8'b0001_0100;
end
end
end
S7:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S8;
time_left <= 5'd4;
led <= 8'b0001_0100;
end
else
begin
state <= S7;
time_left <= time_left-1'b1;
led <= 8'b0001_0010;
end
end
end
S8:begin
if(clkout)
begin
if(time_left==0)
begin
state <= S1;
time_left <= 5'd14;
led <= 8'b1000_0001;
end
else
begin
state <= S8;
time_left <= time_left-1'b1;
led <= 8'b0001_0100;
end
end
end
endcase
end
end
else
begin
state <= S0;
time_left <= 5'd0;
led <= 8'b0000_0000;
end
endmodule
三、总结
时序仿真结果是正确的，没有经过硬件仿真，需要的话可以自己设置下pin脚，然后自己仿真下试试