一. 状态机理论基础
状态机基本概念:
状态机类型:
一、二、三段式状态机各自的优缺点:
状态机质量指标
二.Verilog实现状态机例子
2.1FSM实现实现11010110序列输出
状态机设计
module FSM_gener(
input clk,
input rst_n,
output reg data_current
);
//变量分配定义
reg [3:0] state_current;
reg [3:0] state_next;
reg data_next;
localparam //使用格雷码,减少数据翻转,减小误码率和功耗
IDEL = 4'b0000,
ONE = 4'b0001,
TWO = 4'b0011,
THREE = 4'b0010,
FOUR = 4'b0110,
FIVE = 4'b0111,
SIX = 4'b0101,
SEVEN = 4'b0100,
EIGHT = 4'b1100;
//第一段状态机,时序逻辑状态更新
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
state_current <= IDEL;
else
state_current <= state_next;
end
//第二段状态机,组合逻辑状态判断跳转
always@( * ) begin
case( state_current )
IDEL:begin
state_next <= ONE;
data_next <= 1'b0;
end
ONE:begin
state_next <= TWO;
data_next <= 1'b1;
end
TWO: begin
state_next <= THREE;
data_next <= 1'b1;
end
THREE:begin
state_next <= FOUR;
data_next <= 1'b0;
end
FOUR:begin
state_next <= FIVE;
data_next <= 1'b1;
end
FIVE:begin
state_next <= SIX;
data_next <= 1'b0;
end
SIX: begin
state_next <= SEVEN;
data_next <= 1'b1;
end
SEVEN:begin
state_next <= EIGHT;
data_next <= 1'b1;
end
EIGHT:begin
state_next <= IDEL;
data_next <= 1'b0;
end
default:begin
state_next <= IDEL;
data_next <= 1'b0;
end
endcase
end
//第三段状态机,时序逻辑数据输出
always@( posedge clk or negedge rst_n ) begin
if( !rst_n )
data_current <= 1'b0;
else
data_current <= data_next;
end
endmodule
仿真验证
`timescale 1ns/1ns
`define clock_period 20
module FSM_gener_tb();
reg clk;
reg rst_n;
wire data_current;
FSM_gener FSM_gener0
(
.clk(clk),
.rst_n(rst_n),
.data_current(data_current)
);
initial begin clk = 1'b1; end
always#( `clock_period ) clk = ~clk;
initial begin
rst_n = 0;
#( `clock_period*10 );
rst_n = 1;
#( `clock_period*10 + 1'b1 );
#( `clock_period*50 );
$stop;
end
endmodule
仿真结果如下所示,状态机循环输出11010110满足设计要求
2.2 连续字符串"aebf"检测
。。。待补充