记录学习日常，先试一下静态数码管我的开发板上有六个数码管，一个数码管上有八段。上代码：

module seg(
	input clk,
	input rst_n,
	output reg [5:0]sel,
	output reg [7:0]seg
);

reg flag;
parameter Time = 250;
reg [24:0]cnt;
reg [3:0] state;

always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		flag <= 1'b0;
		cnt <= 25'd0;
	end
	else if(cnt < Time - 1)begin
		cnt <= cnt + 1'b1;
		flag <= 1'b0;
		end
	else begin
		cnt <= 25'd0;
		flag <= 1'b1;
	end
	
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		state <= 4'd0;
	else if(flag)begin
		if(state < 4'hf)
			state <= state + 1'b1;
	else
		state <= 4'h0;
	end
		
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		sel <= 6'b111111;
	else
		sel <= 6'b000000;
		
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		seg <= 8'b0000_0000;
	else begin
		case (state)
			4'h0 : seg <= 8'b1100_0000;
			4'h1 : seg <= 8'b1111_1001;
			4'h2 : seg <= 8'b1010_0100;
			4'h3 : seg <= 8'b1011_0000;
			4'h4 : seg <= 8'b1001_1001;
			4'h5 : seg <= 8'b1001_0010;
			4'h6 : seg <= 8'b1000_0010;
			4'h7 : seg <= 8'b1111_1000;
			4'h8 : seg <= 8'b1000_0000;
			4'h9 : seg <= 8'b1001_0000;
			4'ha : seg <= 8'b1000_1000;
			4'hb : seg <= 8'b1000_0011;
			4'hc : seg <= 8'b1100_0110;
			4'hd : seg <= 8'b1010_0001;
			4'he : seg <= 8'b1000_0110;
			4'hf : seg <= 8'b1000_1110;
			default : seg <= 8'b1100_0000;
		endcase
	end

endmodule

设置个计数器让数码管0.5秒翻转一次，并给一个技术满标志，再加一个16位的状态state。

仿真代码

`timescale 1ns/1ns
`define clock_period 20

module seg_tb;

	reg clk;
	reg rst_n;
	wire [5:0]sel;
	wire [7:0]seg;

seg u_seg(
	 .clk(clk),
	 .rst_n(rst_n),
	 .sel(sel),
	 .seg(seg)
);
initial clk = 1;
always#(`clock_period/2)clk = ~clk;
initial begin
	rst_n = 1'b0;
#(`clock_period*20)
	rst_n = 1'b1;
	#200000;
		$stop;
		end
		
		endmodule
		

 哈哈，第一次写的我连位选和段选都分不清，以及在数码管中1对应1111_1001都不清楚。记录下，以后应该不会忘了。