module fsm(
    input    wire    clk,
    input    wire    rst,
    input    wire    key1,
    input    wire    key2,
    input    wire    [3:0]water1,
    input    wire    [3:0]wtaer2,
    output    reg        [3:0]led);

parameter c10s=500_000_000;
reg [31:0]    cnt;

parameter    [6:0]IDLE=7'b0000001;
parameter    [6:0]M005=7'b0000010;    
parameter    [6:0]M100=7'b0000100;
parameter    [6:0]M105=7'b0001000;
parameter    [6:0]M200=7'b0010000;
parameter    [6:0]LED1=7'b0100000;
parameter    [6:0]LED2=7'b1000000;
reg [6:0]state;

always @(posedge clk or posedge rst) begin
    if (rst==1) begin
        state<=IDLE;    
    end
    else  case (state)
                IDLE:if(key1==1)
                        state<=M005;
                        else if(key2==1)
                        state<=M100;
                M005:if(key1==1)
                        state<=M100;
                        else if(key2==1)
                        state<=M105;
                M100:if(key1==1)
                        state<=M105;
                        else if(key2==1)
                        state<=M200;
                M105:if(key1==1)
                        state<=M200;
                        else if(key2==1)
                        state<=LED1;
                M200:if(key1==1)
                        state<=LED1;
                        else if(key2==1)
                        state<=LED2;
                LED1:if(cnt==c10s)
                        state<=IDLE;
                LED2:if(cnt==c10s)
                        state<=IDLE;
                default:state<=IDLE;
        endcase
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        cnt<=0;
    end
    else if (cnt>=c10s) 
        cnt<=0;
        else 
            cnt<=cnt+1;
    end


always @(posedge clk or posedge rst) begin
    if (rst==1) begin
        led<=4'b0000;
    end
    else if (state==IDLE) begin
        led<=4'b0000;
    end
    else if(state==M005)
        led<=4'b0001;
    else if(state==M100)
        led<=4'b0010;
    else if(state==M105)
        led<=4'b0100;
    else if(state==M200)
        led<=4'b1000;
    else if(state==LED1)
        led<=water1;
    else if(state==LED2)
        led<=wtaer2;        
end


endmodule

module single_led(
    input    wire    clk,
    input    wire    rst,
    output    reg    [3:0]led=4'b0001);
parameter    cnt_end=25_000_000;
reg    [31:0]    cnt;
reg    led_flag;
reg    [3:0]led_shift;
always @(posedge clk or posedge rst) begin
    if (rst) begin
        
    end
    else if (cnt>=cnt_end) begin
        cnt<=0;
    end
    else begin
        cnt<=cnt+1;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        led_flag<=0;
    end
    else if (cnt==cnt_end) begin
        led_flag<=1;
    end
    else begin
        led_flag<=0;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        led<=4'b0001;
    end
    else if (led_flag==1) begin
        led<={led[2:0],led[3]};
    end
end

endmodule

module single_led(
    input    wire    clk,
    input    wire    rst,
    output    reg    [3:0]led=4'b0001);
parameter    cnt_end=25_000_000;
reg    [31:0]    cnt;
reg    led_flag;
reg    [3:0]led_shift=4'b0001;
reg    rl_flag=0;//左移右移标志        low=left  high=right
always @(posedge clk or posedge rst) begin
    if (rst) begin
        
    end
    else if (cnt>=cnt_end) begin
        cnt<=0;
    end
    else begin
        cnt<=cnt+1;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        led_flag<=0;
    end
    else if (cnt==cnt_end) begin
        led_flag<=1;
    end
    else begin
        led_flag<=0;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        led<=4'b0001;
    end
    else if (led_flag==1&&rl_flag==0) begin
        led<={led[2:0],led[3]};
    end
    else if(led_flag==1&&rl_flag==1)begin
        led<={led[0],led[3:1]};
    end
    else begin
        led<=led;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        rl_flag<=0;
    end
    else if (led==4'b1000) begin
        rl_flag<=1;
    end
    else if(led==4'b0001)begin
        rl_flag<=0;
    end
    else begin
        rl_flag<=rl_flag;
    end
end

endmodule

module    debounce(
    input    wire    clk,
    input    wire    rst,
    input    wire    key,
    output    wire    op_key);

parameter cnt_end=250_000;
reg [31:0]cnt;
reg    cnt_flag;
reg key_flag;
always @(posedge clk or posedge rst) begin
    if (rst==1) begin
        cnt<=0;
    end
    else if (key==0) begin
        cnt<=cnt+1;
    end
    else begin
        cnt<=0;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst==1) begin
        cnt_flag<=0;
    end
    else if(key==1) begin
        cnt_flag<=0;
    end
    else if (cnt==cnt_end) begin
        cnt_flag<=1;
    end
end

always @(posedge clk or posedge rst) begin
    if (rst==1) begin
        key_flag<=0;
    end
    else if (cnt_flag==1&&cnt==cnt_end) begin
        key_flag<=1;
    end
    else begin
        key_flag<=0;
    end
end

assign op_key =key_flag ;
endmodule