1.Data on the I2Sn_RX pin is shifted serially into the Receive Shift Register and then copied into the Receive Buffer Register.The data is then copied to I2Sn Receive Left/Right Data n Registers.

2.On I2S, the frame is marked by a whole clock cycle of the frame sync signal with 50% duty cycle.

3.Data for the left channel is transferred first followed by the right channel data.

4.When the I2S module is enabled, MSB-first data transfer starts when the appropriate level is detected on the frame-sync clock.

5.Setting the PACK bit field in the I2SSCTRL register enables data packing in the 32-bit I2S data registers for word-lengths of 8, 10, 12, 14 and 16 bits.

6.During the receive operation, the I2S bus puts successive data samples into the I2Sn Receive Left/Right Data n Registers before generating the interrupt/event.

7.