1 要求

1.2 异步verilog代码

module top_module(
    input clk,
    input in,
    input areset,
    output out); //

    parameter A=2‘b00, B=2‘b01, C=2‘b11, D=2‘b10;
     reg [1:0] next_state;
     reg [1:0] state;
    // State transition logic: next_state = f(state, in)
    always @(posedge clk or posedge areset) begin
        if(areset)begin
            state <=A;
        end
        else begin
            state <= next_state;
        end
        
    end
    always @(*)begin
        case (state)
            A: begin
                if(in==1‘b1)begin
                    next_state = B ;
                end
                else begin
                    next_state = A;
                end end
            B: begin
                if (in==1‘b0) begin
                    next_state = C;
                end
                else begin
                    next_state = B;
                end end
            C: begin
                if (in==1‘b1) begin
                    next_state = D;
                end
                else begin
                    next_state =A;
                end  end
            D: begin
                if (in==1‘b1) begin
                    next_state = B;
                end
                else begin
                    next_state =C;
                end  end

            default: next_state = A;
        endcase     
    end


    // Output logic:  out = f(state) for a Moore state machine  只和当前的状态有关和输入无关
    assign out =(state == D)?1‘b1:1‘b0;

endmodule

1.3 仿真图

1.4 原理图

已知状态表写状态机