A Brief Intro to Verilog by Sat Garcia  verilog Tutorial => Getting started with verilog (riptutorial.com)

 

Ways To Use Verilog:

• Structural/Lower Level has all the details in it (which gates to use, etc), is always synthesizable
• Functional/Higher Level, Easier to write, Not always synthesizable

RTL有两个不同的含义: In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices. RTL is the earliest class of transistorized digital logic circuit used; other classes include diode–transistor logic (DTL) and transistor–transistor logic (TTL).

   

 为啥不画个方框，里面写上AND, &之类，要这么花哨？花得过这个不？

 

Material Design不能简单地归纳为平面化设计（Flat Design）。实际上，Android 4.0的设计风格，也不是纯粹的平面化设计，在经过仔细观察之下，我们可以看到Android 4.0在细节上并没有反对高光、阴影、纹理，换言之它并不反对立体感。不过，它也不能归类为拟物化设计，毕竟它所使用的图案、形状并非是对现实实体的模拟，而是按照自己对数字世界的理解，以色彩、图案、形状进行视觉信息上的划分。[百度百科] Material Design Lite，简洁惊艳的前端工具箱。 - Jason-node - 博客园