NET clk LOC=p24 | IOSTANDARD=LVCMOS33;
NET rst LOC=p93 | IOSTANDARD=LVCMOS33;
NET key LOC=p94 | IOSTANDARD=LVCMOS33;
NET led[0] LOC=p92 | IOSTANDARD=LVCMOS33;
NET led[1] LOC=p87 | IOSTANDARD=LVCMOS33;
NET led[2] LOC=p55 | IOSTANDARD=LVCMOS33;
NET led[3] LOC=p59 | IOSTANDARD=LVCMOS33;

module key_test(
    input    wire    clk,
    input    wire    rst,
    input    wire    key,
    output    wire    [3:0]led);
reg [3:0]    led_shift= 4‘b0001;
reg            key_reg;
always @(posedge clk or negedge rst) begin
    if (rst==0) begin
        key_reg<=1;
    end
    else 
        key_reg<=key;
    
end


always @(posedge clk or negedge rst) begin
    if (rst==0) begin
        led_shift<=4‘b0001;
    end
    else if (key==0&&key_reg==1) begin
        led_shift<={led_shift[2:0],led_shift[3]};
    end
end

assign led = led_shift;
endmodule