Build this LFSR. The reset should reset the LFSR to 1

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5‘h1
    output reg [4:0]  q
); 

always @(posedge clk) begin
    if(reset==1‘b1)begin
        q <= 5‘h1;
    end
    else begin
        q <= {0^q[0],q[4],q[3]^q[0],q[2:1]};
    end
end

endmodule

测试波形

原理图：

HDLbits——Lfsr5