`timescale 1ns / 1ps

 //////////////////////////////////////////////////////////////////////////////////

 // Company:

 // Engineer: chensimin

 //

 // Create Date: 2017/12/14 17:15:25

 // Design Name:

 // Module Name: glitch_filter_1

 // Project Name:

 // Target Devices:

 // Tool Versions:

 // Description:

 //

 // Dependencies:

 //

 // Revision:

 // Revision 0.01 - File Created

 // Additional Comments:

 //

 //////////////////////////////////////////////////////////////////////////////////

 module glitch_filter_1 #(

     parameter WIDTH               = ,

     parameter CNT_CLK_FREQUENCY   = )            // frequency cnt_clk in MHz

 (

     input  wire                     cnt_clk,

     input  wire    [WIDTH-:]      delay_time_high,

     input  wire    [WIDTH-:]      delay_time_low,

     input  wire                     clk,

     input  wire                     rst,

     input  wire                     sign_src,

     output wire                     sign_src_filter

 );

     localparam UNLOCK = 'b0;

     localparam LOCK   = 'b1;

     reg get_time_1us;

     reg [WIDTH-:]m;

     always @ ( posedge cnt_clk or posedge rst )

     begin

         if( rst )

         begin

             get_time_1us <= 'b0;

             m <= ;

         end

         else if( m == CNT_CLK_FREQUENCY -  )

         begin

             get_time_1us <= 'b1;

             m <= ;

         end

         else

         begin

             get_time_1us <= 'b0;

             m <= m + 'b1;

         end

     end

     reg [WIDTH-:]i;

     reg [WIDTH-:]k;

     reg get_delay_time_high;

     reg get_delay_time_low;

     reg current_state;

     reg next_state;

     always @ ( posedge cnt_clk or posedge rst )

     begin

         if( rst )

         begin

             get_delay_time_high <= 'b0;

             get_delay_time_low <= 'b0;

             i <= ;

             k <= ;

         end

         else

         begin

             get_delay_time_high <= 'b0;

             get_delay_time_low <= 'b0;

             case( current_state )

             UNLOCK:

                 if( sign_src == 'b1 )

                 begin

                     if( i == delay_time_high -  )

                     begin

                         get_delay_time_high <= 'b1;

                         i <= ;

                     end

                     else if( get_time_1us )

                     begin

                         i <= i + 'b1;

                     end

                 end

                 else

                 begin

                     i <= ;

                 end

             LOCK:

                 if( sign_src == 'b0 )

                 begin

                     if( k == delay_time_low -  )

                     begin

                         get_delay_time_low <= 'b1;

                         k <= ;

                     end

                     else if( get_time_1us )

                     begin

                         k <= k + 'b1;

                     end

                 end

                 else

                 begin

                     k <= ;

                 end

             endcase

         end

     end

     always @ ( posedge cnt_clk or posedge rst )

     begin

         if( rst )

             current_state <= UNLOCK;

         else

             current_state <= next_state;

     end

     always @ ( * )

     begin

         case( current_state )

         UNLOCK:

             if( get_delay_time_high == 'b1 )

                 next_state = LOCK;

             else

                 next_state = UNLOCK;

         LOCK:

             if( get_delay_time_low == 'b1)

                 next_state = UNLOCK;

             else

                 next_state = LOCK;

         endcase

     end

     reg sign_src_r;

     always @ ( posedge cnt_clk or posedge rst )

     begin

         if( rst )

             sign_src_r <= 'b0;

         else

         begin

             case( current_state )

             UNLOCK:

                 sign_src_r <= 'b0;

             LOCK:

                 sign_src_r <= 'b1;

             endcase

         end

     end

     reg [:]sign_src_r_delay;

     always @ ( posedge clk or posedge rst )

         if(rst)

             sign_src_r_delay <= 'b00;

         else

             sign_src_r_delay <= {sign_src_r_delay[], sign_src_r};

     assign sign_src_filter = sign_src_r_delay[];

 endmodule

 /*

 add_force {/glitch_filter_1/cnt_clk} -radix hex {0 0ns} {1 50000ps} -repeat_every 100000ps

 add_force {/glitch_filter_1/rst} -radix hex {1 0ns} {0 100000ps}

 add_force {/glitch_filter_1/sign_src} -radix hex {0 0ns} {1 198000ps} {0 232000ps} {1 308000ps} {0 354000ps} {1 400000ps} {0 450000ps} {1 552000ps} {0 2550000ps} {1 2740000ps} {0 2850000ps} {1 2950000ps} {0 3550000ps}

 add_force {/glitch_filter_1/delay_time_high} -radix hex {4 0ns}

 add_force {/glitch_filter_1/delay_time_low} -radix hex {5 0ns}

 add_force {/glitch_filter_1/clk} -radix hex {0 0ns} {1 25000ps} -repeat_every 50000ps

 */