题目：实现数码管动态扫描功能，将十六个开关的值以十六进制的方式在4个数码管上同时显示出来。
`timescale 1ns / 1ps module top(
clk, sw, seg, an
);
//FPGA时钟
input [:] sw; // 16位拨动开关，其中SW[0]可用于作为复位信号rst
input clk;
output [:] seg; // 8段数码管驱动，低电平有效
output [:] an; // 8段数码管片选信号，低电平有效
wire [:] data; //待显示内容
wire clk1000Hz, clk100Hz, clk10Hz, clk1Hz;//1000/100/10/1Hz的时钟
FrequencyDivider U_FRQNCYDVD(clk, clk1000Hz, clk100Hz, clk10Hz, clk1Hz);//分频器
SevenSegDisp U_DISP(clk1000Hz, sw,seg, an);
module FrequencyDivider (clk, clk1000Hz, clk100Hz, clk10Hz, clk1Hz);//分频器
input clk; // 系统时钟
output reg clk1000Hz; // 分频后的时钟1000Hz
output reg clk100Hz; //分频后的时钟100Hz
output reg clk10Hz; //分频后的时钟10Hz
output reg clk1Hz; // 分频后的时钟1Hz
parameter N1000 = 50_000; // 1000Hz的时钟,N=fclk/fclk_N
parameter N100 = 50_000_0; // 1000Hz的时钟,N=fclk/fclk_N
parameter N10 = 50_000_00; // 1000Hz的时钟,N=fclk/fclk_N
parameter N1 = 50_000_000; // 1Hz的时钟,N=fclk/fclk_N
reg [:] counter1000, counter100, counter10, counter1; /* 计数器变量，通过计数实现分频。
当计数器从0计数到(N/2-1)时，
输出时钟翻转，计数器清零 */
always @(posedge clk) begin // 时钟上升沿
if(counter1000==N1000) begin
clk1000Hz <= ~clk1000Hz;
counter1000 <= 'h0;
end
else
counter1000 <= counter1000 + ;
end always @(posedge clk) begin // 时钟上升沿
if(counter100==N100) begin
clk100Hz <= ~clk100Hz;
counter100 <= 'h0;
end
else
counter100 <= counter100 + ;
end always @(posedge clk) begin // 时钟上升沿
if(counter10==N10) begin
clk10Hz <= ~clk10Hz;
counter10 <= 'h0;
end
else
counter10 <= counter10 + ;
end always @(posedge clk) begin // 时钟上升沿
if(counter1==N1) begin
clk1Hz <= ~clk1Hz;
counter1 <= 'h0;
end
else
counter1 <= counter1 + ;
end
endmodule
`timescale 20ms / 1ms
module SevenSegDisp(clk,sw,seg,an);
input clk;
input [:] sw; // 16位拨动开关
output [:] seg; // 7段数码管驱动，低电平有效
output [:] an; // 7段数码管片选信号，低电平有效 reg [:] q;
wire [:] data;
initial
begin
q='b00;
end
// Counter8 U_CNT(clk,q);
always @(posedge clk ) begin
q<=q+;
if (q=='b11) q= 2'b00;
else q = q;
end Mem U_MEM (q,sw,data);
Decoder3_8 U_D38(q, an); //片选
SevenSegDecoder U_SSD1(data,seg); //8段码 endmodule
`timescale 20ms / 1ms module Mem (num,sw,data);
input [:] num;
input [:] sw;
output [:] data;
reg [:] mem [:];
// initial
// begin
// assign sw=16'h0000;
// end
assign data = mem[num];
always @(*) begin
mem[] = sw[:];
mem[] = sw[:];
mem[] = sw[:];
mem[] = sw[:];
end endmodule
`timescale 20ms / 1ms module Decoder3_8(num, sel);
input [: ] num; // 数码管编号：0~7
output reg [:] sel; // 7段数码管片选信号，低电平有效 always @(num) begin
case(num)
'd0: sel = #10000000 8'b11111110;
'd1: sel = #10000000 8'b11111101;
'd2: sel = #10000000 8'b11111011;
'd3: sel = #10000000 8'b11110111;
default: sel = 'b11111111;
endcase
end endmodule
module SevenSegDecoder(
data, segments
);
input [:] data;
output [:] segments; assign segments = {dp, cg, cf, ce, cd, cc, cb, ca}; reg dp, cg, cf, ce, cd, cc, cb, ca;
always @(data) begin
case(data)
'h0: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0000_0011;
'h1: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b1001_1111;
'h2: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0010_0101;
'h3: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0000_1101;
'h4: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b1001_1001;
'h5: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0100_1001;
'h6: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0100_0001;
'h7: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0001_1111;
'h8: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0000_0001;
'h9: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0001_1001;
'ha: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0001_0001;
'hb: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b1100_0001;
'hc: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b1110_0101;
'hd: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b1000_0101;
'he: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0110_0001;
'hf: {ca, cb, cc, cd, ce, cf, cg, dp} = 8'b0111_0001;
default: {ca, cb, cc, cd, ce, cf, cg, dp} = 'b1111_1111;
endcase
end endmodule
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform { } [get_ports {CLK}];
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[] }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[]
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L13N_T2_MRCC_14 Sch=sw[]
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L12N_T1_MRCC_14 Sch=sw[]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L7N_T1_D10_14 Sch=sw[]
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[]
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L5N_T0_D07_14 Sch=sw[]
set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[] }]; #IO_L24N_T3_34 Sch=sw[]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[] }]; #IO_25_34 Sch=sw[]
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[]
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[]
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L24P_T3_35 Sch=sw[]
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[]
set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[] }]; #IO_L21P_T3_DQS_14 Sch=sw[]
## segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { seg[] }]; #dp
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[] }]; #an[]