目录
- 1、Wire
- 2、GND
- 3、NOR
- 4、Another gate
- 5、Two gates
- 6、More logic gates
- 7、7420 chip
- 8、Truth tables
- 9、Two-bit equality
- 10、Simple circuit A
- 11、Simple circuit B
- 12、Combine circuits A and B
- 13、Ring or vibrate
- 14、Thermostat
- 15、3-bit population count
- 16、Gates and vectors
- 17、Even longer vectors
- 参考资料：https://hdlbits.01xz.net/
1、Wire
module top_module (
input in,
output out);
assign out = in;
endmodule
2、GND
module top_module (
output out);
assign out = 1'b0;
endmodule
3、NOR
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
4、Another gate
module top_module (
input in1,
input in2,
output out);
assign out = in1 & (~in2);
endmodule
5、Two gates
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
6、More logic gates
Ok, let’s try building several logic gates at the same time. Build a combinational circuit with two inputs, a and b.
There are 7 outputs, each with a logic gate driving it:
out_and: a and b
out_or: a or b
out_xor: a xor b
out_nand: a nand b
out_nor: a nor b
out_xnor: a xnor b
out_anotb: a and-not b
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & (~b);
endmodule
7、7420 chip
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
8、Truth tables
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = ((~x3) & x2) | (x3 & x1);
endmodule
9、Two-bit equality
Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.
module top_module ( input [1:0] A, input [1:0] B, output z );
assign z = (A==B)?1'b1:1'b0;
endmodule
10、Simple circuit A
Module A is supposed to implement the function z = (x^y) & x. Implement this module.
module top_module (input x, input y, output z);
assign z = (x^y) & x;
endmodule
11、Simple circuit B
module top_module ( input x, input y, output z );
assign z = ~(x ^ y);
endmodule
12、Combine circuits A and B
module top_module (input x, input y, output z);
wire z1;
wire z2;
assign z1 = (x^y)&x;
assign z2 = ~(x^y);
assign z = (z1 | z2) ^ (z1 & z2);
endmodule
13、Ring or vibrate
Suppose you are designing a circuit to control a cellphone’s ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.
在顺序程序中，通常是：如果输入为（input are_），然后输出为（output are_），而在硬件电路中是：当输入为（input are_）时，输出为（output are_），硬件中的是从输出去判断输入（有这个输出，但是这个输出是有条件的）。
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & (~vibrate_mode);
assign motor = ring & vibrate_mode;
endmodule
14、Thermostat
A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.
The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = (~mode) & too_hot;
assign fan = (mode & too_cold) | ((~mode) & too_hot) | fan_on;
endmodule
15、3-bit population count
A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 3-bit input vector.
module top_module(
input [2:0] in,
output [1:0] out );
integer i;
always@(*) begin
out = 2'b00;
for(i=0;i<3;i=+i+1)
out = out + in[i];
end
endmodule
16、Gates and vectors
You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:
out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are ‘1’. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
integer i;
always@(*) begin
for(i=0;i<3;i=i+1) begin
out_both[i] = in[i] & in[i+1];
out_any[i+1] = in[i] | in[i+1];
out_different[i] = in[i] ^ in[i+1];
end
out_different[3] = in[0] ^ in[3];
end
endmodule
17、Even longer vectors
You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:
out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are ‘1’. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[99].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_both = in[98:0] & in[99:1];
assign out_any = in[99:1] | in[98:0];
assign out_different = in[99:0] ^ ({in[0],in[99:1]});
endmodule