数字系统设计实验1

二选一电路设计

ENTITY first IS
  PORT ( a, b, s: IN  BIT; 
              y : OUT BIT  );
END ENTITY first;
ARCHITECTURE one OF first IS
      SIGNAL d,e :  BIT;
  BEGIN
   d <= a AND (NOT S); 
   e <= b AND s;  
   y <= d OR e;
END ARCHITECTURE one ; 

四选一电路设计

ENTITY first IS
  PORT ( a, b,c,d,s1,s2: IN  BIT; 
              y : OUT BIT  );
END ENTITY first;
ARCHITECTURE one OF first IS
      SIGNAL f,g,h,i :  BIT;
  BEGIN
   f <= a AND (NOT s1) and (NOT s2);
	g <= b AND (NOT s1) AND s2;
	h <= c AND s1 AND (NOT s2);
   i <= d AND S1 AND S2;
   y <= f OR g OR h OR i;
END ARCHITECTURE one ;