FPGA错误整理

一,assign和always语句中的变量赋值

1,object "count_clr" on left-hand side of assignment must have a net type

                这个意思是assign语句只能对wire型变量赋值。

2,Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type
                在always块语句里只能是reg型变量赋值。

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