• 代码

module mux21(
              input s,
	input a,
	input b,
	output reg y
             );				 
always@(s or a or b)
begin
     if (~s) begin
	      y<=a;
	  end else begin
	      y<=b;
	  end
			
    end
endmodule



`timescale 1ns/1ns
module mux21_tst();
reg s;
reg a;
reg b;
wire y;
parameter PERIOD1 = 2; 
parameter PERIOD2 = 50; 
initial begin
s=1'b0;a=1'b0;b=1'b0;
#(PERIOD2*20) s=1'b0;
#(PERIOD2*20) s=1'b1;
//#(PERIOD2*1600) $stop;
end
always begin
#(PERIOD1/2) a= ~a;
end
always begin
#(PERIOD2/2) b= ~b;
end
mux21 u1(.s(s),
                  .a(a),
                  .b(b),
                  .y(y));
endmodule

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