02_led_blink_v3

本段代码是为Verilog初学者提供的一个名为led_blink简单实例Verilog模块，其功能是控制6个LED灯同步闪烁，每秒钟闪烁一次。

与02_led_blink_v2版本相比新增内容：

1. 使用一个特定位宽的count变量控制多个LED的速度，与之前版本不同，本例代码中，6个led可以以不同的速度闪烁，呈现更丰富的效果，为后续跑马灯，流水灯和呼吸灯做准备，同学们要重点理解变量位宽的概念和位宽的确定方法。

2. 使用Verilog的位拼接语法，组合各个led不同的闪烁速度

知识点：

• 位拼接，位截取
• 确定变量的位宽

module led_blink #(
    parameter ONE_MSECOND = 50*1000,    //clock periods of one millsecond
    parameter ALL_LED_ON  = 6'b000000   //led active low
)(
    input  clk,   
    input  rst,

    input wire [5:0] dip_u5,
    output reg [5:0] led
);

//
localparam COUNT_MAX = ONE_MSECOND * 1000; // = 50000000

//(50000000)D = (0010 1111 1010 1111 0000 1000 0000)B
reg [25:0] count; 

//count will wrap to zero when equal to 26'h3FFFFFF
//so count will be update for zero to 26'h3FFFFFF, then to zero and recycle
always @(posedge clk) count <= count + 1;

//1: get bits from reg or wire vector
wire msb_bit  = count[25]; 
wire [1:0] msb_2bits = count[25:24]; 

//2: three method to get continuous bits from a vector
//wire [5:0] msb_6bits = count[25:20];
wire [5:0] msb_6bits = count[25 -: 6];
//wire [5:0] msb_6bits = count[20 +: 6];

//3: combine any bits from one or multi vectors 
wire [5:0] any_6bits = {count[25:24],count[20:18],count[23]}; 
wire [5:0] any_6bits_dip = {{count[25 -: 3]},dip_u5[2 +: 3]}; 

//4. in always block, you can also combine any bits
always @(posedge clk) begin
    //led <= {6{msb_bit}}; 
    //led <= {3{msb_2bits}};
    led <= msb_6bits;
    //led <= {msb_bit, msb_bit, msb_bit,msb_bit,msb_bit,msb_bit}; 
    //led <= any_6bits;
    //led <= any_6bits_dip;
end

endmodule