/*********************************************

  ** Clocks & Reset

  *********************************************/

  `define CLOCK_FREQ    200e6  //时钟频率

  `define RESET_TIME    

  reg clk;

  initial clk = 'b0;

  localparam CLOCK_PERIOD = 1e9/`CLOCK_FREQ;

  always

    #(CLOCK_PERIOD) clk = ~clk;

  reg reset;

  initial begin

    reset = 'b1;

    #(`RESET_TIME);

    @(posedge clk);

    reset = 'b0;

  end

    @(posedge clk);

    if (o_tvalid) begin

      $display("Test 1 FAILED!");

      $error("o_tvalid still asserted after emptying FIFO!");

      $stop;

    end

使用相反控制信号inout口，等于两个模块之间用inout双向口互连。

这种方法要注意assign 语句只能放在initial和always块内。 

module test(); 

wire data_inout;

reg data_reg;

reg link;

initial

begin .......... end

assign data_inout=link?data_reg:'bz; 

endmodule